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Topic: Silicon on insulator

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	Silicon-on-insulator optical waveguide Michelson interferometer sensor for temperature monitoring - Patent 6603559
		Silicon is very easy to acquire and very cheap, and has been the major material in the IC manufacturing process, so the present invention uses silicon-on-insulator as the substrate.
		Silicon-on-insulator waveguide Bragg grating 2 comprises an amorphous silicon layer 21, a sinusoidal silicon grating layer 22, a silicon dioxide insulating layer 16 and a silicon substrate 17, as shown in FIG.
		By the couple-mode equation, the present invention designed an optimal silicon-on-insulator waveguide Bragg grating having waveguide width 11 of 6.mu.m, sinusoidal silicon grating layer 22 of 1.5.mu.m, grating period 23 of 0.2215.mu.m, grating length 24 of 100.mu.m, silicon dioxide insulation layer 16 of 0.4.mu.m, and amorphous silicon layer 21 of 1.mu.m.
	www.freepatentsonline.com /6603559.html (2127 words)

	Silicon on insulator - Wikipedia, the free encyclopedia
		Silicon on insulator (SOI) is a layered structure consisting of a thin layer of silicon, from 50 nm to 100 µm, which is created on an insulating substrate, which is usually sapphire or silicon with an insulating layer of silicon dioxide(SiO
		The advantage is that this insulator reduces the capacitance, meaning the transistor has less to charge-up before completing a switch, which results in reduced switching time.
		The thin layer of silicon that is left behind is isolated from the substrate by what was originally the surface oxide layers.
	en.wikipedia.org /wiki/Silicon_on_insulator (425 words)

	Silicon On Insulator from Compart Technology, the supplier UK of Silicon On Insulator
		Silicon On Insulator from Compart Technology will be just what you need for your project or research.
		Our service is the ultimate in Silicon On Insulator for people who have been disappointed by their Silicon On Insulator suppliers before or those new to the field of Silicon On Insulator.
		Silicon On Insulator : Growing a silicon ingot can take anywhere from one week to one month, depending on many factors, including size, quality and the end users specifications.
	www.silicon-wafers.co.uk /insulator.html (756 words)

	Encyclopedia :: encyclopedia : Silicon on insulator (Site not responding. Last check: 2007-10-06)
		Silicon on insulator (SOI) is a layered structure consisting of a thin layer of silicon, from 50 nm to 100 µm, which is created on an insulating substrate, which is usually sapphire or silicon with an insulating layer of silicon dioxide 80 nm thick on its surface.
		A popular SOI technology is Silicon on sapphire (SOS), used in special rad-hard applications in military and aerospace.
		Smartcut is another method that bonds the oxidized surface of two wafers together and then splits most of the top wafer away along a band of implanted hydrogen bubbles.
	www.hallencyclopedia.com /Silicon_on_insulator (380 words)

	Silicon on Insulator (SOI) definition - Semiconductor Technology
		Silicon on insulator (SOI) is a semiconductor wafer technology.
		SOI is a fabrication technique that uses pure crystal silicon and silicon oxide for integrated circuits and microchips.
		Silicon on insulator allow for process performance and lower power leakage to be improved.
	www.semiconductor-technology.com /glossary/silicon-on-insulator.html (70 words)

	Soitec, world's leading manufacturer and supplier of SOI wafers for the semiconductor industry
		The silicon chain begins with the pulling of monocrystalline ingots and the slicing of these ingots into wafers.
		The circular, silicon wafers that are delivered to semiconductor manufacturers range in diameter from a few inches up to today’s latest dimension of 300mm (12”).
		The role of SOI is to electronically insulate a fine layer of the monocrystalline silicon from the rest of the silicon wafer.
	www.soitec.com /en/techno/t_1.htm (309 words)

	Secret of 'strained silicon' chips revealed - 20 December 2003 - New Scientist (Site not responding. Last check: 2007-10-06)
		In ordinary silicon, all six orbitals have the same energy so there is no preferred direction of flow.
		Transistors contain regions of silicon that are doped with a material such as phosphorus to create an excess of electrons in the conduction band - "n-doped" silicon - and regions that are doped with boron, which adds positively-charged holes to form "p-doped" silicon.
		Because silicon nitride contracts less than silicon as it cools, it locks the silicon lattice beneath it in place with a wider spacing than it would normally adopt.
	www.newscientist.com /article.ns?id=dn4493 (660 words)

	IBM Blue Logic Silicon-on-Insulator
		IBM's announcement is significant because, while others, including IBM, have been successful in developing SOI technology, IBM is the first to be able to apply it in building fully-functional mainstream microprocessors, the most complex type of chip.
		This new IBM success in harnessing SOI technology will result in faster computer chips that also require less power--a key requirement for extending the battery life of small, hand-held devices that will be pervasive in the future.
		SOI is a major breakthrough because it advances chip manufacturing one to two years ahead of conventional bulk silicon.
	www-03.ibm.com /chips/about/technology/technologies/soi (266 words)

	ViewTouch: Silicon On Insulator and Copper Interconnectivity
		IBM implants a thin, 3,500-angstrom layer of oxide beneath a silicon layer of1,800 angstrom on a non-epitaxial wafer.
		SOI refers to a thin layer of silicon placed on top of an insulation layer, such as silicon oxide or glass, which reduces the transistor capacitance that consumes power and slows the chip dthat consumes power and slows the chip down.
		Using this new technology, a silicon wafer of completed circuits is placed on a thermal chuck with an extremely flat surface.
	www.viewtouch.com /soi.html (2898 words)

	SOI: Silicon-On-Insulator
		Silicon-On-Insulator (SOI), developed by IBM, is a chipmaking technology that builds transistors on a thinner layer of silicon than previously possible, improving chip performance and reducing power consumption.
		SOI is a layered structure consisting of a thin layer of silicon, from 50 nm to 100 µm, which is created on an insulating substrate, which is usually sapphire or a silicon with an insulating layer of silicon dioxide 80 nm thick on its surface.
		This process reduces the amount of electrical charge that the transistor has to move during a switching operation, increasing speed (up to 15%) and reducing switching energy (up to 20%) over CMOS-based chips.
	www.javvin.com /hardware/SOI.html (119 words)

	© AMDboard.com - AMD & SOI (Silicon on insulator) Special
		"Innovative Silicon Inc. (ISi), a startup pioneer of "floating-body" memory, has come up with an improved version of the technique that provides a factor of ten improvement in the 1 to 0 margin and the data retention time.
		With the local approach, strained silicon becomes part of the device architecture and is included in the CMOS process, whatever the SOI substrate or bulk wafer.
		AMD had problems with its silicon on insulator die designs last year and at the beginning of this.
	www.amdboard.com /soispecial.html (1480 words)

	Silicon-on-insulator technology optimizes in-vehicle networking
		SOI literally adds a layer of insulation to the substrate under the top silicon in which the transistors are built, and this makes a world of difference.
		Conventional bulk silicon chips have transistors directly on the silicon substrate (bottom) where they are subject to current leakage.
		All devices in bulk silicon are isolated by such p-n junctions, but their thickness grows with operating voltage.
	www.embedded.com /shared/printableArticle.jhtml?articleID=181500644 (1780 words)

	Silicon-on-Insulator - a Whatis.com definition
		Silicon-On-Insulator (SOI) is a semiconductor fabrication technique developed by IBM that uses pure crystal silicon and silicon oxide for integrated circuits (ICs) and
		When IBM began developing SOI chips, they found it difficult to bond the insulator layer of the chip, which was a non-crystal substance, to the pure crystal silicon layer.
		This layer of silicon oxide film is perfect enough that it bonds with the pure crystal silicon layer.
	searchnetworking.techtarget.com /gDefinition/0,294236,sid44_gci551314,00.html (428 words)

	Photonics.com \| Search (Site not responding. Last check: 2007-10-06)
		difference in refractive index between silicon and air (Δn = 2.45) or between silicon and silicon dioxide (Δn = 2.0).
		Silicon Laser Relies on Quantum Wells Silicon-based lasers have been much...
		believe to be the first silicon laser, a feat that exploits...
	www.photonics.com /photonicsFind.aspx?searchString=silicon-on-insulator&searchIndex=0 (349 words)

	UMC Announces a Device Technique that Enhances Silicon-on-Insulator (SOI) Transistor Performance
		Silicon-on-Insulator is an approach in which transistors are built on top of an insulating material instead of the conventional silicon crystal substrate.
		By replacing the silicon substrate with an insulator substrate, extra capacitive load produced at the interface between the substrate and the transistor active areas is eliminated.
		However, the body of the transistor is now sitting on an insulator and therefore electrically isolated from the rest of the circuit.
	www.us.design-reuse.com /news/news7936.html (640 words)

	IBM Research \| Press Resources \| IBM paves way for higher performing, lower power electronic devices
		Also, IBM is the first to combine two different underlying silicon layers that simultaneously maximize the performance of the key transistors used in complementary metal oxide semiconductor (CMOS) devices, which are the foundation for everything from cell phones to PCs to supercomputers.
		Strained silicon technology provides high electron mobility by stretching the top silicon layer with an underlying layer of silicon germanium (SiGe).
		A strained silicon (Si) directly-on-insulator structure is fabricated by a layer transfer technique.
	domino.research.ibm.com /comm/pr.nsf/pages/news.20030909_cmos.html (758 words)

	Nanometer-scale silicon-on-insulator photonic componets (US5838870)
		A multi-layer core for the strip consistes of several 1-3 nanometer crystal silicon multiple quantum wells confined by wide bandgap epitaxial barriers.
		The MQW region of the strip employs intersubband or band-to-band photonic effects.
		(c) a silicon substrate having an upper surface portion underlying the lower surface portion of said dielectric insulating layer.
	www.delphion.com /details?&pn=US05838870__ (261 words)

	Amazon.com: Silicon-On-Insulator (Site not responding. Last check: 2007-10-06)
		Proceedings of the Fifth International Symposium on Silicon-On- Insulator Technology and Devices (Proceedings Ser.; Vol.
		SOI is Silicon On Insulator- on the top of an...
		Buy Silicon on Insulator Wafers at Sqi -- Buy silicon on insulator wafers from Silicon Quest International, a full service supplier of silicon wafers and related services.
	www.amazon.com /s?ie=UTF8&search-alias=aps&keywords=Silicon-On-Insulator&page=1 (564 words)

	AMD, IBM announce semiconductor manufacturing technology breakthrough (Site not responding. Last check: 2007-10-06)
		AMD and IBM today announced that they have perfected a new strained silicon transistor technology aimed at improving processor performance and power efficiency.
		AMD plans to ship 90nm AMD Athlon™ 64 products that use the new strained silicon technology beginning in the first quarter of 2005. AMD also plans to gradually integrate it into all of its 90nm processor platforms, including its multi-core AMD64 processors.
		IBM is a recognized innovator in the semiconductor industry, having been first with advances like more power-efficient copper wiring in place of aluminum and faster SOI and silicon germanium transistors.
	www-03.ibm.com /chips/news/2004/1213_amd.html (355 words)

	IBM taps new technology to build faster chips \| CNET News.com
		As previously reported, SOI is one of a recent spate of chip manufacturing ideas from IBM.
		Other advances include the use of copper and an advanced insulation material called "low-k" dielectrics, the use of which IBM announced in April.
		Additionally, the glass used in the chip must be as pure and defect-free as standard silicon, Zieber said.
	news.com.com /2100-1001-240856.html (836 words)

	Electronic transport in nanometre-scale silicon-on-insulator membranes : Nature
		When this silicon layer (the template layer) is very thin, the assumption that an effectively infinite number of atoms contributes to its physical properties no longer applies, and new electronic, mechanical and thermodynamic phenomena arise
		The development of unusual electronic properties with decreasing layer thickness is particularly important for silicon microelectronic devices, in which (001)-oriented SOI is often used
		Here we show—using scanning tunnelling microscopy, electronic transport measurements, and theory—that electronic conduction in thin SOI(001) is determined not by bulk dopants but by the interaction of surface or interface electronic energy levels with the 'bulk' band structure of the thin silicon template layer.
	www.nature.com /nature/journal/v439/n7077/abs/nature04501.html (269 words)

	Silicon Photonics, Papers and Articles - Technology & Research at Intel
		Intel scientists are making breakthroughs in silicon photonics by developing silicon-based optical devices that could one day be mass produced alongside Intel microprocessors.
		Learn more about how Intel is driving silicon photonic innovations that could lead to high-speed optical connections for computers as well as new, affordable devices for biomedical and scientific applications.
		Liu, D. Samara-Rubio, L. Liao, and M. Paniccia, "Scaling the Modulation Bandwidth and Phase Efficiency of a Silicon Optical Modulator," IEEE Journal of Selected Topics in Quantum Electronics, 11, 2, 367-372 (2005).
	www.intel.com /technology/silicon/sp/doc.htm (795 words)

	SOI technology for the GHz era
		In the early 1990s, SOI development was transferred to the Advanced Silicon Technology Center (ASTC) of the IBM Microelectronics Division, with the goal of serious assessment of SOI CMOS and increased focus on 8-in.
		One manifestation of the threshold variation is the “kink effect,” or increase in the output conductance of the device near drain-to-source bias, V
		, of 1 V, the bandgap of silicon [1].
	www.research.ibm.com /journal/rd/462/shahidi.html (4009 words)

	Honeywell's Silicon On Insulator Technology (Site not responding. Last check: 2007-10-06)
		Honeywell's foundry, gate arrays and ASICs are based on Silicon On Insulator (SOI) technology that incorporates a silicon dioxide insulator.
		As a result, density is significantly increased and risks of field failure are reduced.
		If you compare Silicon On Insulator with Bulk CMOS between two chips with identical design rules, superior performance of SOI is attained by:
	www.ssec.honeywell.com /aerospace/technologies/soi.html (490 words)

	EETimes.com - Future points to SOI with strained silicon
		In his contribution to the section, Carlos Mazure, chief technology officer of SOI wafer manufacturer Soitec (Grenoble, France), explains how silicon on a fused quartz substrate (SOQ) and silicon on glass will enable ICs to be developed on transparent substrates.
		The challenges of controlling the diffusion of dopants used to form source and drain extensions are detailed in a contribution by a team of Applied Materials and Soitec researchers.
		Soitec CEO, Andre Auberton-Herve, provides an outline of the metrology and manufacturing challenges facing the silicon industry as SOI substrates move to 300-mm diameters and stringent uniformity levels.
	www.eetimes.com /in_focus/silicon_engineering/OEG20020923S0050 (734 words)

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