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| | Applied Research into Space Data Networks Using the SpaceWire Protocol, 15-9472 |
 | | The research component will investigate the required IP stack interface to Spacewire, various IP operational scenarios, onboard network architectures, and define how the IP layer will be implemented onto of the SpaceWire protocol layers. |
 | | Following this initial trade study, the hardware design phase will be broken into five major components, including establishment of a detailed requirements specification, creation of a baseline module design, implementation of board architecture, parts procurement, and fabrication and verification of the module. |
 | | The final deliverables for the hardware phase are a completed and verified SpaceWire module, along with a reusable Verilog logic core capable of being used in future SpaceWire designs. |
| www.swri.org /3pubs/ird2004/Synopses/159472.htm (438 words) |
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