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Topic: Speculative execution

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Superscalar

Central processing unit

	Geeking with Greg: The rise of wildly speculative execution
		Speculative execution sends a processor down the the most likely path of a conditional branch, executing a few cycles of machine instructions that may have to be thrown away if the branch prediction was incorrect.
		What I think we may see is a radically expanded version of speculative execution, running code seconds or minutes ahead of when it may be needed.
		I could imagine a computer immune system that was using a fraction of the processors to search for anomalous patterns in the usage of the rest of the hardware, growing in size as potential threats are detected, shrinking away as the threat passes.
	glinden.blogspot.com /2007/02/rise-of-wildly-speculative-execution.html (0 words)

	Pulse: A Dynamic Deadlock Detection MechanismUsing Speculative Execution (Site not responding. Last check: 2007-10-29)
		During the execution of a speculative process, Pulse records all the events it creates (e.g., releasing a lock or writing to a pipe).
		The next step for the speculative process is to return from the system call that caused its parent to sleep, pretending the call was successful, and then to resume its parent's user-level code after the blocking system call, all within the speculative process's own context (i.e., the parent is unchanged and it continues to sleep).
		The execution of a speculative process should be safe, i.e., it should not modify the state of any other process.
	www.cs.duke.edu /~tongli/projects/usenix05 (9660 words)

	Evaluation of memory control
		Execution times without speculative execution are shown in Figure 6.
		However, the adverse effects of speculative execution can linger for some time after it has been disabled, as the resulting `gap' in memory cannot be immediately filled with useful data.
		In the 72MB and 80MB results, basic speculative execution has enough memory available to provide overall benefit; however, the control mechanism is still able to identify a handful of places where it is beneficial to temporarily disable speculative execution.
	www.usenix.org /events/usenix2003/tech/fraser/fraser_html/node18.html (549 words)

	Speculative Execution
		In the SP machine, a misprediction cancels the execution of all instructions following the branch, so mispredictions are barriers to instruction scheduling.
		The branch constraint for this machine requires that a branch cannot execute before a preceding misprediction.
		To achieve the performance of the ORACLE machine, instructions from alternate paths must be executed simultaneously, and only the instructions from one of the paths will be useful.
	suif.stanford.edu /papers/lam92/subsection3_5_2.html (654 words)

	Speculative execution
		We propose that applications continue executing speculatively after they have issued a read request that misses in the file cache; that is, when they would ordinarily stall waiting for a disk read to complete.
		During this speculative execution, applications should issue the appropriate (non-blocking) hint call whenever they encounter a read request in order to inform the underlying prefetching system that the data specified by that request may soon be required.
		If we assume that speculative execution proceeds at the same pace as normal execution, then, while normal execution is stalled waiting for the first read request to complete, speculative execution may be able to issue hints for the remaining three read requests.
	www.usenix.org /publications/library/proceedings/osdi99/full_papers/chang/chang_html/node4.html (492 words)

	Configurable branch prediction for a processor performing speculative execution - Patent 5454117
		In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information.
		It is possible to perform speculative execution (also known as conditional, or out-of-order execution) past predicted branches, if additional state is provided for backing up the machine state upon mispredicted branches.
		During speculative execution, it is necessary to use predicted branch direction information to supplement the Shift Register output.
	www.freepatentsonline.com /5454117.html (9642 words)

	Data and Control Speculative Execution
		All forms of speculation need to keep a record of speculated events (state) so that they can be rolled back and re-executed if necessary.
		Figure 2 shows the flow of data for the speculative execution of the three loop iterations assuming arbitrary resources.
		Speculation is achieved by treating blocks as independent entities and activating blocks at the same level of the tree in parallel.
	www.cs.waikato.ac.nz /timewarp/wengine/papers/gc99_1 (0 words)

	Instruction pointer limits in processor that performs speculative out-of-order instruction execution - Patent 5740393
		The result data is speculative until the branch prediction that caused speculative execution of the corresponding micro instruction is resolved.
		The writes back of speculative results by the execution circuit 40 is out of order due to the out of order dispatching of physical micro-ops by the reservation and dispatch circuit 38 and the differing number of processor 22 cycles required for execution of the differing types of physical micro-ops.
		The speculative results held in the physical registers of the reorder circuit 42 are committed to an architectural state in the same order as the original logical micro-ops were received.
	www.freepatentsonline.com /5740393.html (14241 words)

	SPEAR - Speculative Pre-Execution Assisited by CompileR
		Speculative pre-execution is a new data-prefetching technique which uses an auxiliary assisting thread in addition to the main program flow.
		Recently, various forms of speculative pre-execution have been developed, including hardware-based and software-based approaches.
		It relies on a "post-compiler" to extract the p-thread code from program binaries and uses specially designed SMT hardware to trigger the execution of the p-thread dynamically.
	pascal.eng.uci.edu /projects/SPEAR (0 words)

	Reducing Misspeculation Overhead for Module-Level Speculative Execution (Site not responding. Last check: 2007-10-29)
		Thread-level speculative execution is a technique that makes it possible for a wider range of single-threaded applications to make use of the processing resources in a chip multiprocessor.
		We consider module-level speculation, i.e., speculative threads executing the code after a module (i.e., a procedure, function, or method) call.
		We show that the overhead when spawning speculative threads for all module continuations is on average three times as big as the time spent on useful execution on our baseline 8-way chip multiprocessor.
	www.ce.chalmers.se /research/group/hpcag/publ/2005/WS05 (0 words)

	WG 10.3 e-Seminar
		Speculative pre-execution achieves efficient data prefetching by running additional prefetching threads on spare hardware contexts.
		Various implementations for speculative pre-execution have been proposed, including compiler-based static approaches and hardware-based dynamic approaches.
		This talk introduces SPEAR (Speculative Pre-Execution Assisted by compileR), a pre-execution model which is a hybrid of the two approaches.
	www.ifipwg103.org /seminar/Gaudiot.htm (0 words)

	[No title]
		Speculative Execution: Dynamically elide the locks Observe the shared memory areas Do speculative memory updates to a write buffer (Speculative memory writes are not done to the cache) Do speculative register updates to a reorder buffer or use register checkpoint Add an access bit to every block on cache to detect conflicts.
		Execution completion¡ª¨èWhen execution inside critical section has completed then results need to be updated to the cache from the write buffer.
		Two types of speculation: 1) control dependences : Reorder code to reduce size of critical section for most common cases or most frequently executed paths at the cost of expensive recovery operation on the less frequently executed paths.
	www.csc.calpoly.edu /~franklin/520/LockCritical.ppt (1963 words)

	SPEAR - Speculative Pre-Execution Assisited by CompileR
		Speculative pre-execution is a new data-prefetching technique which uses an auxiliary assisting thread in addition to the main program flow.
		Recently, various forms of speculative pre-execution have been developed, including hardware-based and software-based approaches.
		It relies on a "post-compiler" to extract the p-thread code from program binaries and uses specially designed SMT hardware to trigger the execution of the p-thread dynamically.
	tamanoir.ece.uci.edu /projects/SPEAR/index.html (186 words)

	Irisa : thèse proposée pour la rentrée 2001
		These mechanisms allow to expose to the compiler a part of the speculative execution that is managed by hardware on current out-of-order execution superscalar processors.
		The goal of the proposed study is to evaluate ISA supports for speculative executiom in the light of state-of- the-art out-of- order execution mechanisms.
		As it features speculative execution support, the IA64 instruction set will be used as a research vehicle for this study.
	www.irisa.fr /theses2001/caps1.htm (467 words)

	Pentium Pro Microprocessor
		It has a three-way superscalar architecture, (executing three instructions per CPU clock) with a pipeline depth of twelve in the multiple execution units (including two for integer operations and one for floating-point operations).
		execution, branch prediction, and speculative execution via register renaming to achieve higher parallelism.
		Dynamic Execution Technology can be summarized as optimally adjusting instruction execution by predicting program flow, having the ability to speculatively execute instructions in any order, and then analyzing the program’s dataflow graph to choose the best order to execute the instruction.
	www.ece.unh.edu /courses/ece707_4/micropentpro.htm (985 words)

	Speculative Execution
		Our simulations of speculative execution use static branch predictions based on profile information.
		A mispredicted branch in a trace is easily identified by comparing the actual branch outcome with the predicted outcome.
		The simulator for the SP machine simply remembers the execution time of the most recent mispredicted branch, and no subsequent instructions in the trace can execute before that time.
	suif.stanford.edu /papers/lam92/subsubsection3_4_4_2.html (0 words)

	Using Speculative Execution to Automatically Hide I/O Latency (Site not responding. Last check: 2007-10-29)
		This trend is causing applications that must fetch data from disk to spend an increasing proportion of their execution times stalled on disk I/O. I/O prefetching, a well-known technique for hiding disk latency, has the potential to alleviate this problem, particularly when the data that needs to be fetched is distributed across multiple disks.
		These added executions skip some operations, like accesses to uncached data, so that they can run ahead of their target normal executions.
		Despite any such differences, the approach predicts that the data accesses encountered during speculative executions will often be the same as the data accesses that will be encountered during their target normal executions such that, by initiating prefetching of that data, speculative executions could reduce the I/O stall time of their target normal executions.
	www.pdl.cmu.edu /PDL-FTP/TIP/CMU-CS-01-172_abs.html (368 words)

	Compaq Fortran
		Speculative execution reduces instruction latency stalls to improve run-time performance for certain programs or routines.
		Speculative execution evaluates conditional code (including exceptions) and moves instructions that would otherwise be executed conditionally to a position before the test, so they are executed unconditionally.
		Indicates that all routines in the current compilation unit (set of routines being compiled) can do speculative execution, but speculative execution will not be performed for routines in other compilation units in the program.
	www.phys.uu.nl /DU/progtool/cf95v53u/dfuum010.htm (2463 words)

	Speculative Execution and Branch Prediction
		In some cases, not all of the results of the execution will be used, because changes in the program flow may mean that the instruction should never have been encountered in the first place.
		More advanced processors will speculatively execute the next instruction anyway, with the hope that it will be able to use the results if the branch goes the way it thinks it will.
		A processor that speculatively executes may start both the addition and subtraction going at the same time, and then simply discard whichever one it turns out not to need.
	www.pcguide.com /ref/cpu/arch/int/featSpeculative-c.html (505 words)

	Computer Laboratory - May 29th 2003
		We present an in-kernel disk prefetcher which uses speculative execution to determine what data an application is likely to require in the near future.
		Not only is our system easier to implement and deploy, but by handling page faults as well as traditional file-access methods we are able to apply speculative execution to swapping applications, which often spend the majority of their execution time fetching non-resident pages.
		These are a fast method for synchronizing an errant speculative process with normal execution, and a modified form of copy-on-write which preserves application semantics without delaying normal execution.
	www.cl.cam.ac.uk /Research/SRG/netos/old_seminars/0203/abstracts/may29.html (255 words)

	Enhancing Multiple-Path Speculative Execution with Predicate Window Shifting
		Speculative execution has long been used as an approach to exploit instruction level parallelism across basic block boundaries.
		Most existing speculative execution techniques only support speculating along single control path, and heavily rely on branch prediction to choose the right control path.
		In this paper, we propose an extended predicated execution mechanism, called predicate shifting, to support speculating along multiple control paths.
	www.cs.umn.edu /tech_reports_upload/1997/TR_97-032__Enhancing_Multiple-Path_Speculative_Execution_with_Predicate_Window_Shifting.html (223 words)

	SpecHint
		We designed a method for transforming application binaries to employ the speculative execution approach using only simple, generic static analyses and transformations.
		The problem is that our initial, naive design makes no attempt to address speculative execution's inherent sensitivity to the amount of inter-read code and the existence of data dependencies in applications.
		With our current implementations, for example, the mean performance improvement with our automatic approach is 47%, 78% and 82% in 1, 2 and 4-disk configurations, respectively, of the mean performance improvement when the applications were manually modified to issue hints.
	www.pdl.cs.cmu.edu /TIP/spechint.html (685 words)

	Automatic I/O Hint Generation through Speculative Execution (Site not responding. Last check: 2007-10-29)
		Aggressive prefetching is an effective technique for reducing the execution times of disk-bound applications; that is, applications that manipulate data too large or too infrequently used to be found in file or disk caches.
		Our approach is to speculatively pre-execute the application's code in order to discover and issue hints for its future read accesses.
		Without any manual modifications, we achieve 29%, 69% and 70% reductions in execution time when the data files are striped over four disks, improving performance by the same amount as manually-hinted prefetching for two of our three applications.
	www.cs.cmu.edu /afs/cs.cmu.edu/project/pdl/ftp/TIP/osdi-distrib-abs.html (347 words)

	AnandTech: Fall IDF 2005 - Day 1: Coverage of Everything
		On modern day Out of Order microprocessors, the CPUs themselves will speculatively execute code based on what it thinks will need to be executed in the future - thus improving processor utilization and overall performance.
		This research project proposes that the same sort of speculative execution be applied on a thread level, meaning that threads are created on the fly and speculatively executed by idle cores in a system in order to improve performance on future multi-core CPUs.
		At the end of the execution of the thread, its result is checked to make sure that the data is still valid, and if so, the result is committed and all is well.
	www.anandtech.com /tradeshows/showdoc.aspx?i=2507&p=7 (667 words)

	Automatic I/O Prefetching Hints through Speculative Execution (Site not responding. Last check: 2007-10-29)
		Many applications, ranging from simple utilities to databases, manipulate data too large or infrequently used to be reliably found in memory caches.
		Due to the huge disparity between processor speeds and disk access times, these disk-bound applications tend to waste a disproportionate percentage of their execution times waiting for disk requests to complete.
		I will describe the design and evaluation of SpecHint, a tool that transforms application binaries to use the speculative execution approach.
	www.cs.berkeley.edu /Seminar.archive/2000/04.Apr/000404.chang.html (183 words)

	UWTV Program: Automatic I/O Prefetching Hints through Speculative Execution
		Many applications, ranging from simple utilities to databases, manipulate data too large or infrequently used to be reliably found in memory caches.
		Due to the huge disparity between processor speeds and disk access times, these disk-bound applications tend to waste a disproportionate percentage of their execution times waiting for disk requests to complete.
		We can hide disk latency from these applications by taking advantage of under-utilized I/O resources to perform prefetching.
	www.uwtv.org /programs/displayevent.aspx?rID=2119&fID=497 (0 words)

	An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors (Site not responding. Last check: 2007-10-29)
		High-performance, out-of-order execution processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction algorithms.
		Although memory references generated on the wrong path do not change the architectural state of the processor, they affect the arrangement of data in the memory hierarchy.
		We also show that it is crucial to model wrong-path references to accurately estimate the performance improvement provided by runahead execution.
	csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/trans/tc/&toc=comp/trans/tc/2005/12/tztoc.xml&DOI=10.1109/TC.2005.190 (770 words)

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