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	Transitive Closure on the Instruction Systolic Array
		The instruction systolic array (ISA) is an array processor architecture, which is characterized by a systolic flow of instructions (instead of data as in standard systolic arrays).
		Systolic solutions for the transitive closure and the shortest path problem are presented by Kung, Lo and Lewis [3].
		The instruction systolic array has been proposed recently in [5] as a parallel processor architecture which is on the one hand suitable for VLSI, since it is a systolic architecture,and which is on the other hand flexible enough for efficiently executing a large variety of different algorithms belonging to quite different problem classes (see e.g.
	www.iti.fh-flensburg.de /lang/papers/trans/transcl.htm (3699 words)

	Reconfigurable systems for sequence alignment and for general dynamic programming
		Reconfigurable systolic arrays can be adapted to efficiently resolve a wide spectrum of computational problems; parallelism is naturally explored in systolic arrays and reconfigurability allows for redefinition of the interconnections and operations even during run time (dynamically).
		Systolic arrays provide a large amount of parallelism and are well adapted to a restricted set of computational problems: those that present strictly regular data dependencies.
		Systolic array restrictions may be circumvented by using reconfigurable circuits, since the same system may be reconfigured in order to deal with different tasks.
	www.funpecrp.com.br /GMR/year2005/vol3-4/wob05_full_text.htm (3088 words)

	Systolic architectures for sonar processing - Patent 4758999
		A three-dimensional systolic architecture for beamforming according to convolve signals from an array with sets of weighting coefficients using a one dimensional array of similar modules with finite impulse response filter elements with outputs directed into pipelining register stacks and propagated to the stack boundaries for summing in accumulator arrays and demultiplexing.
		A three-dimensional systolic architecture according to claim 1 wherein each said FIR filter is adapted to connect to one sensor to receive said broadcast data samples therefrom, whereby each sensor broadcasts its data to one systolic array per module.
		The systolic array is a one, two or higher dimensional array of identical processors.
	www.freepatentsonline.com /4758999.html (2166 words)

	Systolic array (Site not responding. Last check: 2007-09-12)
		By analogy with the regular pumping of blood by the heart, a systolic array is an arrangement of processors in an array (often rectangular) where data flows synchronously across the array between neighbours, usually with different data flowing in different directions.
		One matrix is fed in a row at a time from the top of the array and is passed down the array, the other matrix is fed in a column at a time from the left hand side of the array and passes from left to right.
		At this point, the result of the multiplication is stored in the array and can now be output a row or a column at a time, flowing down or across the array.
	publicliterature.org /en/wikipedia/s/sy/systolic_array.html (278 words)

	Systolic Arrays at Georgia Tech
		FORGE, focal plane architecture for Gigascale Integration, is a systolic array that incorporates focal plane I/O. This research investigates the high performance and efficiency of systolic arrays with consideration to the data flow of planar image sensors.
		Systolic arrays have traditionally provided efficient, high performance execution for computation intensive applications.
		Our research in systolic arrays is focused on incorporating new technological advances to improve node communications, I/O bandwidth, and programmability.
	www.ece.gatech.edu /research/pica/systolic (114 words)

	One dimensional systolic array architecture for neural network - Patent 5799134 (Site not responding. Last check: 2007-09-12)
		It is a further object of the invention to provide a neural network circuit comprising a one dimensional systolic array of processing elements which is controlled by a microprocessor (or other controller); which controller selects between radial based and weighted sum neurons by transmitting a control signal to the systolic array.
		It is also an object of the invention to provide a neural network circuit in the form of a one dimensional systolic array which utilizes pipelined processing and partitioning to achieve a highly efficient data flow in the neural network circuit.
		The one dimensional systolic array also includes an activation function circuit for receiving the accumulated values g.sub.i sequentially from the shift register and for outputting a sequence of values Y.sub.i =S(g.sub.i), where S is an activation function.
	www.freepatentsonline.com /5799134.html (3534 words)

	Game of Life Simulator (Site not responding. Last check: 2007-09-12)
		This type of neighboring cell relationship suggests a systolic array implementation of processors, each representing a single cell, and designed to compute its next state based on the state of its neighbors.
		The absent neighbors of the cells on the outer edge of the grid are assumed to be dead.
		Eight columns are then put side by side to form the entire array, and the single column inverters are all driven by a large single inverters whose inputs are the input signals to the array.
	web.mit.edu /~mwaldon/www/gameoflife.htm (1506 words)

	Systolic array - Wikipedia, the free encyclopedia
		The Data streams entering and leaving the ports of the array are generated by auto-sequencing memory units (ASMs).
		The systolic array paradigm, data-stream-driven by data counters, is the counterpart of the von Neumann paradigm, instruction-stream-driven by a program counter (also see von Neumann or von Neumann architecture).
		Kung and Charles E. Leiserson published the first paper describing systolic arrays in 1978; however, the first machine known to have used the technique was the Colossus Mark II in 1944.
	en.wikipedia.org /wiki/Systolic_array (458 words)

	SASMC and PAMSAC (Site not responding. Last check: 2007-09-12)
		SASMC is the first systolic array chip for the group.
		The first design principle of systolic arrays is to use simple modular cells was set to cope with increased design complexity.
		The systolic core cells are tiled (4x8) to form a 2-D processing core.
	www.ece.gatech.edu /research/pica/systolic/pamsac.html (314 words)

	Computer Science 294-7, Lecture #9 (Site not responding. Last check: 2007-09-12)
		A systolic architecture uses a regular array composed of a few simple compute-cells which exchange pipelined data with their adjacent neighbors at clocked intervals.
		Inputs streams A & B traverse up & down the array (respectively), with record fields staggered so that the fields belonging to a single record from the A stream and a single record from the B stream are compared by a single row of the array.
		For large data sets, the systolic array structure can typically be segmented into "bands" (with respect to one of the data sets), so that a single band's worth of hardware can sequentially process the entire array's data set.
	www.cs.caltech.edu /~andre/courses/CS294S97/notes/day9/day9.html (1268 words)

	Brown CS: Tech Report CS-91-34
		Systolic arrays can solve computationally intensive problems many times faster than traditional computers or supercomputers.
		The Systolic Shared Register architecture preserves the simple communication of single-purpose systolic arrays while providing a fully programmable systolic co-processor.
		With the aid of NSL, several systolic applications are examined in detail, in particular sequence comparison problems from the Human Genome Project.
	www.cs.brown.edu /publications/techreports/reports/CS-91-34.html (262 words)

	A Systolic Array Implementation Using FPGAs \| COTS Journal
		One such implementation is the systolic array, composed of an array of separate processing cells.
		A pair of systolic arrays may be used to solve the linear least-squares problem that arises in a wide range of signal processing situations.
		The main (triangular) array is used to implement a pipelined sequence of Givens rotations, which reduces the data matrix, X(n), to upper triangular form by unitary transformations (QR decomposition).
	www.cotsjournalonline.com /home/article.php?id=100249 (753 words)

	Design and Analysis of a Systolic Array for Neural Computation
		Systolic arrays have been proposed in 1979 as a means to fully exploit the possibilities of VLSI.
		Since systolic arrays are pipelined systems, it is important to avoid emptying and refilling them too often, in order to keep the hardware utilization rate high.
		Finally, the use of systolic arrays as neural accelerators is discussed in the light of the experience acquired with the GENES IV array and the MANTRA I machine.
	diwww.epfl.ch /w3lami/team/viredaz/abs/Viredaz94b.html (1844 words)

	Systolic array for solving cyclic loop dependent algorithms (US4698751)
		A systolic array (1) for reducing the time required to solve an algorithm having cyclic loop dependency, i.e., nested loops in which values calculated by inner loops depend upon indices of said inner loops and upon indices of outer loops.
		The array (1) comprises a chain of several identical serially connected and sequentially accessed cells.
		A systolic array for solving an algorithm having cyclic loop dependency, in which two nested loops are executed n and m times, respectively; and the systolic array solves the algorithm in n+m+1 steps said array comprising:
	www.delphion.com /details?pn10=US04698751 (585 words)

	Systolic Array Implementations for Reconfigurable Learning Machines on Transputers, 1991 (Site not responding. Last check: 2007-09-12)
		Abstract: A systolic array implementation for a Reconfigurable Learning Machine (RLM) in the Occam 2 language (executed on transputers) is proposed.
		Central to our implementation of RLM is both the computation of a general Weighted Levenshtein Distance (WLD) using a known systolic array algorithm and substring matching.
		We propose a new algorithm for substring matching based on this systolic array as well as a general method to represent the properties of systolic arrays, in particular the two dimensional, hexagonal systolic array in the Occam 2 language.
	www.cs.utep.edu /~bdauriol/publications/node7.html (211 words)

	An Improved Systolic Array for String Correction (Site not responding. Last check: 2007-09-12)
		Abstract: The theory of systolic automata has served in the past for comparative assessments of the computational power of different systolic arrays.
		Here, it is used in the design of a systolic array.
		Theorems from the theory of systolic automata guide the transformational improvement of a known systolic array for string correction.
	www.lfcs.inf.ed.ac.uk /reports/91/ECS-LFCS-91-153 (52 words)

	A Systolic Array for Pyramidal Algorithms (Site not responding. Last check: 2007-09-12)
		We present a systolic array which performs pyramidal algorithms.
		The array is two-dimensional with one processor per image pixel; the number of steps in its execution is independent of the size of the image.
		The derivation of the array is governed by a mechanical method whose input is a Pascal-like program.
	www.lfcs.inf.ed.ac.uk /reports/90/ECS-LFCS-90-114 (106 words)

	Brown CS: Tech Report CS-92-22
		This work builds upon an existing systolic array for computing the edit distance between two sequences.
		The alignment array is meant to be used as the second phase in a two-phase design, with a modified edit distance array serving as the first phase.
		Because of the extensive pipelining in the systolic array, computing an alignment on the array takes that same amount of time as computing just the edit distance.
	www.cs.brown.edu /publications/techreports/reports/CS-92-22.html (112 words)

	Journal of Xidian University
		Systolic Array of Eigen Value Extraction mainly employs the QR iteration, but the computation cost of QR iteration for a normal matrix is big.
		In this paper, a new array structure is proposed.
		It is easy for this array to realize global synchronized control and interface between different arrays.
	www.ifp.uiuc.edu /~yuhuang/eigensystolic.htm (108 words)

	SPIB - Signal Processing Information Base (Site not responding. Last check: 2007-09-12)
		Here, a different route is taken, by trying to implement the RLS problem on a systolic array, which is also useful for several other applications, such as SVD updating and Kalman filtering.
		A novel systolic array is described for recursive least squares estimation based on the method of 'inverse updating' or 'square root covariance updating'.
		The array is similar to the well known Gentlemen & Kung array for triangular updating, but unlike the latter, it performs a complete RLS computation.
	spib.rice.edu /spib/spib (332 words)

	The KressArray
		A Datapath Synthesis System) for the rDPA (reconfigurable Datapath Array) is a generalization of the systolic array.
		The systolic array is a coarse grain pipe network.
		During the 80ies and later the research in systolic arrays had been dominated by mathematicians.
	www.kressarray.de (357 words)

	CS337(T) Final Project
		And Duane contributed an array of Tri-stated Buffers to reorder the Buses.
		Our Systolic Array can be used to implement some fast parallel matrix multiplication algorithm, or can be used in building a parallel sorting network.
		And with the extension of the cipher described in "The Iak Block Cipher" [PS] or [PDF], we can use the Array to implement a multi-round encryption in a systolic manner.
	www.cs.caltech.edu /~kchen/systolic/index.html (413 words)

	Demonstration of a bidirectional full-systolic convolution array (Site not responding. Last check: 2007-09-12)
		This applet will demonstrate how Y(3) is computed by this systolic array, where x-data and y-data move at the same velocity but in opposite directions.
		This convolution algorithm is implemented using a bidirectional full-systolic convolution array, using 4 processors (n=4).
		Therefore, the utilization of the computational resources of the array is only 50%.
	www.cs.rug.nl /~petkov/SPP/CONVOLUTION (352 words)

	Implementing a Generic Systolic Array for Genetic Algorithms - Bland, Megson (ResearchIndex)
		The systolic design provides high throughput and unidirectional pipelining by exploiting the implicit parallelism in the genetic operators.
		The design is significant because, unlike other hardware genetic algorithms, it is independent of both the fitness function and the particular chromosome length used in a problem.
		Implementing a generic systolic array for genetic algorithms.
	citeseer.ist.psu.edu /bland96implementing.html (638 words)

	What Is A Systolic Array (Site not responding. Last check: 2007-09-12)
		Processor array for speeding comparison of biological sequences using a parameterized version of the rigorous Smith Waterman algorithm from the IRISA Rennes FR.
		FPGA based Systolic Array Processor for Compressed Image (A separate web site is devoted to this project) The objective of this project is implementation of systolic array architectures in hardware Input buffering requirements of a Systolic Array for the Inverse Discrete Wavelet Transform (Abstract) Robert Lang University of Newcastle Andrew Spray University of Newcastle p.
		on a mesh connected parallel computer Computing on a systolic screen: hulls and contours and applications Computational geometry and VLSI Separabilty of sets of polygons A one dimensional systolic array The instruction systolic array (ISA monitor) is an architectural concept for array computers suited to very high integration technology.
	www.nomadworldtrucktour.com /what-is-a-systolic-array.htm (219 words)

	Asynchronous data coprocessor utilizing systolic array processors and an auxiliary microprocessor interacting therewith ...
		An intermediate data bus with a microprocessor and further random access memory communicating with that bus, carries input and output data for the array, input and output data for the microprocessor, and addresses for the memories associated with the processors of the array and for the sequencer.
		The control store communicates data to the intermediate bus, and the sequencer receives data from the intermediate bus, with instructions selected from the control store further providing control signals for the sequencer, the microprocessor, the intermediate bus, the further random access memory, and the input/output bus.
		System which cooperatively uses a systolic array processor and auxiliary processor for pixel signal enhancement
	www.delphion.com /details?pn=US05708830__ (316 words)

	Work Description
		By and by systolic arrays came to be used widely to solve problems that could be characterized by what are called recurrence equations.
		Methods were developed whereby problems that could be characterized by recurrences were solvable using systolic arrays.
		Further, the method is geared towards generating a solution for a general n-dimensional virtual array which is then transformed to fit a real interconnection pattern.
	www.tcs.tifr.res.in /~basant/pers/natureOfWork.html (983 words)

	Brown CS: Tech Report CS-89-32
		We have found that many systolic algorithms can be expressed in such a fashion.
		The Brown Systolic Array (B-SYS) is an embodiment of this philosophy.
		B-SYS is as highly parallel array of simple processing elements tuned for solving combinatorial problems, including sequence comparison.
	www.cs.brown.edu /publications/techreports/reports/CS-89-32.html (96 words)

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