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	Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system - ...
		The method for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 4, further including the step of suspending execution of instructions within each of said plurality of processors until such time as coherency is achieved with respect to all pending read and write operations within said system memory.
		The system for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 11, further including means for suspending execution of instructions within each of said plurality of processors until such time as coherency is achieved with respect to all in pending read and write operations within said system memory.
		The system for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 12, further including means for purging all instructions within each of said plurality of processors in response to achievement of coherency with respect to all pending read and write operations within said system memory.
	www.freepatentsonline.com /5437017.html (5387 words)

	Buffer
		Riparian buffer zones - Riparian Buffer Zones (sometimes called riparian buffer areas) are a type of headwater, riparian zone, or riparian strips which interacts with both slope runoff and stream/river water and are usually independent of the surrounding land use.
		Riparian buffer zones are used to lessen the impacts of surrounding land use on the stream.
		Buffer overflow - In computer security and programming, a buffer overflow is an anomalous condition where a process attempts to store more data in a buffer than there is memory allocated for it, causing the extra data to overwrite adjacent memory locations.
	www.mtogdensci.com /buffer.html (763 words)

	TLB: Translation look-aside buffer (Site not responding. Last check: 2007-09-17)
		Translation Lookaside Buffer (TLB) is cache in a CPU that contains parts of the page table which translate from virtual into real addresses.
		This buffer has a fixed number of entries and is used to improve the speed of virtual address translation.
		The buffer is typically a content addressable memory (CAM) in which the search key is the virtual address and the search result is a real or physical address (which, perversely, may not be the same thing).
	www.javvin.com /hardware/TLB.html (146 words)

	Data processing unit with a TLB purge function - United States Patent 4,849,881
		In TLB purge processing, A TLB is indexed by the upper data from the counter so that for the contents of the corresponding entry, an upper address space identifier, an upper segment number, an upper page number, and a valid flag are connected to a TLB hit detector.
		a third gate for producing a translation lookaside buffer hit signal indicating whether or not the real address data from said translation lookaside buffer is the intended real address data on the basis of the output signals from said first and second gates and the validity-specifying flag from said translation lookaside buffer.
		a fourth gate for producing a translation lookaside buffer hit signal indicating whether or not the real address data from said translation lookaside buffer is the intended real address data on the basis of the output signals from said first, second and third gates and the validity-specifying flag from said translation lookaside buffer.
	xrint.com /patents/us/4849881 (10090 words)

	MEMORY-RELEVANT PORTIONS OF THE PROCESSOR (Site not responding. Last check: 2007-09-17)
		A trap occurs because translation is missing in the translation lookaside buffer (TLB, discussed shortly).
		Ideally the TLB would be large enough to hold translations for every page of physical memory; however this is prohibitively expensive; instead the TLB holds a subset of entries from the page directory table (PDIR) in memory.
		A TLB miss occurs if the page is not translated in the TLB; if the translation is also not in the PDIR, HP-UX uses the page fault code to fault it in.
	docs.hp.com /en/5965-4641/ch01s05.html (3435 words)

	Translation Lookaside Buffer - Wikipedia, the free encyclopedia
		A Translation Lookaside Buffer (TLB) is a cache in a CPU that is used to improve the speed of virtual address translation.
		A TLB has a fixed number of entries containing parts of the page table which translate virtual addresses into physical addresses.
		With hardware TLB management, the CPU itself walks the page tables to see if there is an entry for the specified virtual memory address.
	en.wikipedia.org /wiki/Translation_Lookaside_Buffer (633 words)

	Background fetching of translation lookaside buffer (TLB) entries - Patent 6851038
		The fetching of TLB descriptors from memory by implementing a background processing of TLB descriptors enhances system performance by minimizing operating delays that are caused by the memory management unit (MMU) halting operation of the microprocessor while retrieving TLB descriptors.
		TLB 38 comprises a cache of 32 virtual tag/physical address pairs of the most recent virtual-to-physical address translations which have been identified from a currently executing task.
		This TLB fetch is made in anticipation of a cache miss that is made to the same virtual page as the previous cache hits that caused a TLB miss.
	www.freepatentsonline.com /6851038.html (4174 words)

	OSDI 2002: Practical, transparent operating system support for Superpages
		TLB coverage is defined as the amount of memory accessible through these cached mappings, i.e., without incurring misses in the TLB.
		Figure 1 depicts the TLB coverage achieved as a percentage of main memory size, for a number of Sun and SGI workstation models available between 1986 and 2001.
		The contribution of instruction TLB misses to the total number of misses was found to be negligible in all of the benchmarks.
	www.cs.rice.edu /~ssiyer/r/superpages/osdi02superpages (10443 words)

	CS 537 Notes
		A translation buffer is used to store a few of the translation table entries.
		TLBs are a lot like hash tables except simpler (must be to be implemented in hardware).
		When there is a miss in the TLB, the operating is notified (via an interrupt) and TLB miss-handler is invoked.
	www.cs.wisc.edu /~bart/537/lecturenotes/s17.html (922 words)

	VM System Support (Site not responding. Last check: 2007-09-17)
		TLB miss exceptions thrown by a CPU result in a lookup for mappings in the shared page tables.
		A typical TLB page entry includes a number of bits such as V and ACC signifying whether the page translation is valid, and what the access rights to the page are, along with the physical page number.
		Whereas the TLB is a high-speed associative memory, the TPT is usually implemented as a DRAM module on the NIC board.
	www.eecs.harvard.edu /~magoutis/bsdcon02/html/node11.html (1233 words)

	Memory address translation system having modifiable and non-modifiable translation mechanisms (US5255384)
		Address translation logic, comprised of mutually exclusive modifiable and nonmodifiable translation logic, selectively provides real address output responsive to the externally supplied virtual address from the processor.
		The modifiable translation logic includes modifiable read-write memory, while the non-modifiable translation logic includes fixed combinational logic for providing predefined translations of predetermined virtual addresses to real addresses.
		always preventing the dynamic address translation step whenever one of the predetermined virtual addresses is to be translated and the computing system is operating in the supervisor mode.
	www.delphion.com /details?pn10=US05255384 (876 words)

	The IBM eServer z990 microprocessor
		These buffers are ECC-protected and hold the data of an entire instruction until it is checkpointed, when it can be released and sent to the L2 cache (the maximum amount of store data for a single hardware-implemented instruction is 256 bytes).
		The translator unit comprises a new control concept to ease the implementation of the complicated algorithms for dynamic address and access-register translation in a virtual guest environment.
		However, if it misses in the TLB and has to translate a virtual address, it is allowed to continue as long as the page index (or indices in the event of a pageable guest) needed for translation does not match the page index that was saved from the prior broadcast IPTE.
	www.research.ibm.com /journal/rd/483/slegel.html (8536 words)

	HP-UX Memory Management White Paper (Site not responding. Last check: 2007-09-17)
		Buffering, paging, and deactivation algorithms optimize disk access and determine when data and code for currently running programs are returned from RAM to disk.
		Because TLB size is limited, it is desirable to use as few entries as possible to translate the largest possible amount of memory.
		A trap occurs because translation is missing in the translation lookaside buffer (TLB).
	docs.hp.com /en/1218/mem_mgt.html (10753 words)

	Final Project
		The color of the page changes from green (for new page in the TLB) to yellow if it is a TLB hit where the process has access to either read or write the pages.
		When a virtual address is presented to the MMU for translation, the hardware first checks to see if its virtual page number is present in the associative memory by comparing it to all the entries simultaneously.
		At all times, there are lines connecting the TLB pages to the VM pages they are mapped to, and also a line connecting the running process to the TLB page it is accessing.
	www.csc.villanova.edu /~rkumar/profin.html (1584 words)

	Operating Systems: Nachos - Virtual Memory (Site not responding. Last check: 2007-09-17)
		First, we use a software-managed translation lookaside buffer (TLB) as a cache for page tables to provide the illusion of fast access to virtual page translation over a large address address space.
		But if the mapping is not in the TLB (a TLB ``miss''), page tables and/or segment tables are used to determine the correct translation.
		If the valid bit is clear or if the virtual page is not found in the TLB, a software page table is needed to tell whether the the page is in memory (with the TLB to be loaded with the translation), or the page must be brought in from disk.
	www.cs.columbia.edu /~hgs/teaching/os/hw/vm.html (1486 words)

	Cordless Buffer
		Buffer credits - Buffer credits, also called buffer-to-buffer credits (BBC) are used as a flow control method by Fibre Channel technology and represent the number of frames a port can store.
		Second cordless buffer and third handsets can be placed in other rooms with no phone jacks.
		This was translated into the late 1990s some mice point to begin producing accessory computer electronics home should have run OS-9 operating system in 1984 did the...
	www.mtogdensci.com /cordlessbuffer.html (1035 words)

	POWER3: The next generation of PowerPC processors
		The IPU and IFU are responsible for fetching, caching, and managing the flow of instructions during their tenure in the microprocessor (the tenure of a given instruction begins when it is dispatched to an execution unit and ends when it is completed).
		The FPU also includes 32 64-bit floating-point registers and 24 64-bit physical rename registers or “buffers.” All target results of floating-point load and arithmetic instructions are placed in rename registers until the instruction completes (i.e., until the completion stage of the instruction).
		When the LSU finishes with the current line and advances to the next line (which is already in the L1 cache because of prefetching), the prefetch hardware transfers the line which is in the prefetch buffer to the L1 and prefetches the next line into the buffer.
	www.research.ibm.com /journal/rd/446/oconnell.html (7426 words)

	The Translation Lookaside Buffer (TLB) (Site not responding. Last check: 2007-09-17)
		An on-chip hardware translation buffer (TB or TLB) caches recently used virtual-physical translations (ptes).
		A CPU pipeline stage probes the TLB to complete over 99% of address translations in a single cycle.
		If a translation misses in the TLB, the entry must be fetched by accessing the page table(s) in memory.
	www.cs.duke.edu /courses/cps110/spring99/slides/vm/sld005.htm (66 words)

	Parallel access micro-TLB to speed up address translation (US5835962)
		A memory management unit (MMU) includes a translation lookaside buffer capable of simultaneously servicing three requests supplied to the MMU by an instruction cache and two data caches, respectively.
		a plurality of command request buffers, each connected to receive signals from (a) said translation-lookaside-buffer, (b) a plurality of caches, and (c) said plurality of input buffers, wherein said plurality of input buffers are also connected to receive signals from said plurality of caches; and
		arbiter logic, connected to receive signals from said plurality of command request buffers and which selects one of the signals received from said command request buffers and determines which of said signals received from said command request buffers is to be processed.
	www.delphion.com /details?pn10=US05835962 (882 words)

	Virtual Memory
		First, you will use a software-managed translation lookaside buffer (TLB) as a cache for page tables to provide the illusion of fast access to virtual page translation over a large address space.
		If the valid bit is clear or if the virtual page is not found in the TLB, software translation is needed to tell whether the the page is in memory (with the TLB to be loaded with the translation), or the page must be brought in from disk.
		For example, you will have the freedom to choose how to do software translation on TLB misses, how to represent the swap partition, how to implement paging, etc. In each case, we will expect you to come to the design presentation armed with a defensible justification as to why your choices are reasonable.
	www.cs.rit.edu /~icss544/VirtualMemory.html (1602 words)

	Lecture 7 - Caching and TLBs; Caching and Demand Paged Virtual Memory
		The TLB is implemented as a hardware table of frequently used address translations.
		If a match is found, the TLB uses its pointers to the page frame in main memory, allowing immediate retrieval of that page from memory.
		The cache in the MMU, referenced by the TLB, is called a physically addressed cache, because the TLB converts the virtual addresses to physical addresses before checking the cache.
	www-scf.usc.edu /~csci402/crowley/lect7.html (3674 words)

	Organization of Paging in Intel486 (Site not responding. Last check: 2007-09-17)
		The P bit set to 0 indicates that the entry can not be used for address translation; whereas P = 1 indicates that the address can be used for translation.
		Bit 5 is set by the microprocessor for both types of entries before a read/write access occurs to an address covered by the entry.
		During this address translation process descriptor tables are used.
	cs.gmu.edu /cne/modules/vm/red/i486page.html (460 words)

	U.S. Pregrant 20020156962 - Microprocessor having improved memory management unit and cache memory (Site not responding. Last check: 2007-09-17)
		Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed.
		In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted.
		If the memory access operation is not permitted by the permission information of the particular entry of the virtual cache memory, then the translation lookaside buffer may be accessed based on the logical address information of the particular entry of the virtual cache memory.
	cxp.paterra.com /uspregrant20020156962.html (254 words)

	Code Tuning: Seeing Is Believing
		Let's set up another event-based profile, this time looking at the data cache misses (event code 0x41) as counter 0, as in Figure 15, and data translation lookaside buffer misses (event code 0x46) as counter 1, as in Figure 16.
		Because the access patterns for the matrix data jump with big strides, which means that the cache and data translation lookaside buffer aren't preloaded with the right data—and that causes the FPU to stall.
		But more impressively, the number of data translation lookaside buffer misses has dropped by three orders of magnitude, from 145,363 to 163.
	www.devx.com /amd/Article/30190 (1571 words)

	22C:116, Homework 4 Solutions, Fall 2000
		The expected address translation time is 100ns + k(500ns), where k is the probability of a miss in the translation lookaside buffer, assuming that we only begin the memory cycle if we detect a miss.
		Note that, for some memory architectures, it may be possible to begin a memory cycle as we begin checking the lookaside buffer.
		If we get a hit in the lookaside buffer, we abort the memory cycle devoted to address translation.
	www.cs.uiowa.edu /~jones/opsys/fall00/hw/04sol.html (620 words)

	Translation lookaside buffer flush filter
		A TLB flush filter monitors blocks of memory from which address translations have been loaded and cached in the TLB.
		The TLB flush filter is configured to detect if any of the underlying address translations in memory have changed.
		Un TLB rince les blocs de moniteurs de filtre dont de mémoire des translations d'adresses ont été chargées et cachées dans le TLB.
	www.patentalert.com /docs/000/z00058276.shtml (242 words)

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