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	Shift register memory cell having a transmission gate disposed between an inverter and a level shifter - Patent 4651333
		The transmission gates are fed by complementary clock signals to switch a selected one of the gates between a conducting state, to clock a signal through the transmission gate and into the storage circuit associated therewith, and a nonconducting state, to inhibit a signal from coupling into the associated storage circuit.
		The gate electrodes of the transmission gates connected at the inputs of the pair of storage circuits of each memory cell are fed by a pair of complementary clock signals.
		Transmission gate MESFET 42 fully conducts current from drain to source in response to the +0.4 volt signal applied to the gate thereof by the predetermined occurrence of clock.phi..sub.2, thus coupling the data signal to source-follower MESFET 44 and charging inherent capacitances 41, 43, 45.
	www.freepatentsonline.com /4651333.html (8073 words)

	Fast transmission gate switch - Patent 5289062
		5 is a schematic circuit diagram of a transmission gate switch and of a driver and receiver to illustrate the preferred embodiment of the invention.
		1 is a schematic circuit diagram of a conventional transmission gate switch 20 connected to the output of a driver 22 and the input of a receiver 24 at nodes A, B respectively.
		The gate of transistor 102 is controlled by the output of a driver 104 which may include a pair of P-channel and N-channel resistors connected in parallel between node C and the gate of transistor 102.
	www.freepatentsonline.com /5289062.html (3854 words)

	CMOS over voltage-tolerant output buffer without transmission gate (US6208178)
		The source node is the source of a p-channel transistor that drives the gate of a p-channel driver transistor driving the output pad.
		The isolating output buffer is faster because it does not use a transmission gate in the speed path.
		whereby the over-voltage on the output pad is applied to the gate node of the p-channel driver transistor through the fixed-gate transistor, the n-well node, the well-source transistor, and the p-channel transistor in the isolating gate.
	www.delphion.com /details?pn=US06208178__ (508 words)

	Gate Level Modeling Part-I
		The 1st terminal in the list of gate terminals is an output and the other terminals are inputs.
		Transmission gates are bi-directional and can be resistive or non-resistive.
		Transmission gates tran and rtran are permanently on and do not have a control line.
	www.asic-world.com /verilog/gate1.html (371 words)

	Optimized circuit structure for cascading transmission gate circuits and multiplexors
		A method of connecting the drain of the first transmission gate to the gate of second transmission gate to reduce delay is shown.
		With the more recent technologies, the drain of a transmission gate is not allowed to connect directly to the source of a 2nd transmission gate because the behavior of that type of structure is harder to model accurately.
		When cascading 2 levels of transmission gate mux, the output of the first is connected to the gate of the transistors in the 2nd stage instead of the source of the transistors.
	www.priorartdatabase.com /IPCOM/000136631 (453 words)

	Encyclopedia :: encyclopedia : Electric power transmission (Site not responding. Last check: )
		Typically power transmission is between the power plant and a substation in the vicinity of a populated area.
		The separation of transmission and generation functions is one of the factors that contributed to the 2003 North America flout.
		Transmission and distribution losses in the USA were estimated at 7.2% in 1995 1998.
	www.hallencyclopedia.com /Electric_power_transmission (2341 words)

	CMOS transmission-gate demo (Site not responding. Last check: )
		The idea is that a high voltage (logical 1) on its gate activates the n-channel transistors, while the p-channel transistor conducts when a low voltage (logical 0) is applied to its gate.
		On the other hand, both transistors are non-conducting when a low voltage (logical 0) is applied to the gate of the n-channel transistor while a high voltage (logical 1) is applied to the gate of the p-channel transistor.
		In the circuit shown here, the tgate gate input is controlled by input switch S, while the A and B ports of the tgate are connected to a tri-state buffer each.
	tech-www.informatik.uni-hamburg.de /applets/hades/webdemos/05-switched/40-cmos/tgate_print.html (356 words)

	Near-zero propagation-delay active-terminator using transmission gate (US6686763)
		The transmission gate is turned off and does not conduct most of the time, but turns on when a transition is detected on the transmission line, allowing the transmission line to directly drive the load for a short time.
		Once the load is switched beyond a logic threshold voltage, the transmission gate is again turned off and a latch or latching transistors driven by the transmission line continue to drive the isolated load to power or ground voltages.
		Driver transistors are also enabled when the transmission gate is turned on, driving either the output (load) node or the input (transmission line) node with the new data.
	www.delphion.com /details?pn=US06686763__ (502 words)

	Transmission Lines/Gate Delay
		The two most popular representations of the "state" of a transmission line are the voltage/current model, and the forward/reverse wave model.
		From it we may directly derive the voltage/current ratio (that is, the input impedance) at the input to the line.
		Past this point in time, the input impedance of the transmission line/load structure is a function of both line and load.
	www.signalintegrity.com /Pubs/news/1_19.htm (948 words)

	transmission_gate - The Wordbook Encyclopedia
		It is made by the parallel combination of an nMOS and a pMOS transistor with the input at the gate of one transistor (nMOS) being complementary to the input at the gate of the other (pMOS).
		Depending on whether or not there is a voltage on the gate, the connection between the input and output is either low-resistance or high-resistance, respectively.
		However when gate input to the nMOS is '1' and its complementary '0' is the gate input to the pMOS, both are turned on and passes any signal '1' or '0' equally well without degradation.
	www.thewordbook.com /transmission_gate (273 words)

	Reference.com/Encyclopedia/Transmission gate
		It is a good non-mechanical relay, built with CMOS technology.
		Probably more usually known as an analog gate or electronic relay depending on its use.
		A basic CMOS transmission gate consists of two transistors, an nMOS and a pMOS.
	www.reference.com /browse/wiki/Transmission_gate (109 words)

	Welcome to IEEE Xplore 2.0: Delay-Time Modeling for ED MOS Logic LSI
		The operations of the transmission gate are divided into two modes; synchronous mode and asynchronous mode.
		Corresponding to each mode, the transmission gate, the preceding gate, and the succeeding gate have two kinds of delay times.
		To simulate delay times of each gate precisely, models which treat these three logic elements as one primitive element in a logic simulator have been proposed.
	ieeexplore.ieee.org /xpls/abs_all.jsp?isnumber=28425&arnumber=1270030&count=8&index=0 (272 words)

	CMOS D-type transmission-gate latch
		The left transmission gate is enabled when the clock input is high, while the right transmission gate is enabled when the clock input is low.
		Therefore, when the clock input is high, the current value from the data input (D) will propagate through the left transmission gate and through the inverters.
		The latch is transparent, and the output value Q follows the data input value, while NQ generates the inverse of the data input value.
	tams-www.informatik.uni-hamburg.de /applets/hades/webdemos/05-switched/40-cmos/latch.html (397 words)

	Novas Software: Newsletter (Site not responding. Last check: )
		The traditional method to debugging transmission gates is a very tedious and manual process.
		The user needs to display the signal in the schematic, then search the source code to find all the driving signals of the transmission gate, add those signals to the waveform or schematic, and repeat several times.
		Verdi's Transmission Gate Analysis allows the user to easily trace through bidirectional nets and trace their drivers.
	www.novas.com /Support/Newsletter/2004-08-transmission_gate_analysis.html (349 words)

	Transmission Lines/Gate Delay
		The transmission line mathematics therefore simplify into this two-mode formulation.) To answer your question, I am going to start with the forward/reverse model, and then switch gears to the other model to get the final answer.
		When we have a wave traveling in one direction only, the ratio of voltage to current (i.e., the wave impedance) is constant, and equal to the characteristic impedance of the transmission line.
		Generally speaking, if the far-end load has an impedance greater than Z0, the initial effect (when the reflected wave hits the driver) is to raise the effective input impedance of the line.
	www.sigcon.com /Pubs/news/1_19.htm (948 words)

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	The Pain Clinic - About Pain - Pain Mechanisms
		Depending on the settings in the dorsal horn computer (see Gate Theory and Dorsal Horn Sensitisation below), pain signals are also sent upwards in the spinal cord via the Spinothalamic tract (amongst others) to an area in the brain stem (base of the brain) called the thalamus.
		The normal state of affairs is that there are continuous descending signals from the brain to all the dorsal horn computers in the body.
		These descending signals (descending inhibition) keep nearly all of the gates in a closed state, preventing unnecessary sensory information reaching the brain i.e.
	www.painclinic.org /aboutpain-painmechanisms.htm (2276 words)

	CMOS transmission-gate XOR gate
		The first stage of the circuit consists of a basic static inverter, which generates the inverse of input A. Note that the inverse of A is connected to the gate of the transmission-gate n-channel transistor, while A is connected to the gate of the p-channel transistor.
		Therefore, the transmission gate is conducting when A is low, and passes the value of B. This effectively realizes the (!A & B) term of the standard disjunctive expansion of the XOR function.
		Obviously, the two transistors in the center of the schematics form an inverter that calculates !B, and whose output is connected to the output of the XOR gate.
	tech-www.informatik.uni-hamburg.de /research/software/applets/hades/webdemos/05-switched/40-cmos/xor-tgate.html (492 words)

	NEUROPHYSIOLOGY AND MENTAL FUNCTION
		The prefrontal cortex sends inputs to the reticular nucleus of the thalamus, which is able to gate transmission from the thalamus to the rest of the cortex.
		The pulvinar serves a "gating" function -- directing which neurons responding to our sensory experience are to be most activated.
		Can the same be said of the pulvinar, which may "gate" attention but, being subject to outside influence, neither controls consciousness nor is included in consciousness.
	www.benbest.com /science/anatmind/anatmd8.html (5851 words)

	Definition of Transmission gate
		A transmission gate is an electronic element, representing an ideal non-mechanical relay, built with CMOS technology.
		Probably more usually known as an analog gate or electronic relay dependent on use.
		A basic CMOS transmission gate consists of NMOS and PMOS.
	www.wordiq.com /definition/Transmission_gate (147 words)

	ePanorama.net :: View topic - Transmission Gate question
		are on (5v and 0v gate for n/p, respectively).
		would expect (in the steady state) of a floating transmission gate.
		We were never actually told that the circuit was a transmission gate.
	www.epanorama.net /phpBB2/viewtopic.php?t=14634 (2521 words)

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	cadence \| David Grant dot ca
		4-bit CMOS Transmission Gate Conditional Carry Select Adder
		A CMOS Transmission Gate logic style was used to form the multiplexers and XOR gates.
		The layout was done in Cadence using 0.18 µm technology from CMC, and was very compact and achieved a low-area of 802 µm2.
	www.davidgrant.ca /tags/cadence (249 words)

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