Latches are devices which have no clock input and change output state only in response to data input, while flip-flops have data inputs but change output state only in response to a clock input.
The latch is constructed from a pair of cross-coupled NOR (negative OR) logic gates.
A gated D latch is a latch constructed from an SR latch, two additional AND gates, a NOT gate, and two inputs, data (D) and gate (G).
en.wikipedia.org /wiki/Latch (383 words)
Transparent latch: Facts and details from Encyclopedia Topic(Site not responding. Last check: 2007-10-29)
You will find available on the patchboard an octal buffer and an octal transparentlatch (note that these devices are often used to form byte-wide buses but you need only use them to form a 4-bit bus).
When the clock input on the latch is high, the latch is transparent and the outputs Q follow the inputs D (when the output enable is also active).
Design a suitable logic circuit which uses the output of the transparentlatch, and illuminates one of three LEDS to indicate an underfill, an acceptable fill, and an overfill according to the rules above.
The appropriate bits of a microinstruction are supplied from the microinstruction memory to the associated resource via the transparentlatch.
The clock signal for the sequencer or other resource serves as the enable signal for the output latch (which can be either a transparentlatch or an edge-triggered latch resposive to the rising edge of the clock signal), while the inverted sense of the clock signal provides the enable signal for the transparentlatch.
Therefore those set-up conditions can already have been completed (or at least partially completed) before the results of the prior instruction are cleared out of the output latch and the new microinstruction is latched into the input latch.
The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34).
The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent).
The latched outputs remain stable as long as the LEnn is LOW.
www.philipsmcu.com /pip/74HC75.html (334 words)
Single-transistor transparent-latch clocking(Site not responding. Last check: 2007-10-29)
The low power dissipation of the single-transistor latch can therefore be used to improve the gain in architecture-driven voltage scaling where one reduces the supply voltage to reduce power dissipation and applies pipelining to compensate for the reduced speed.
In our example, the fraction of power dissipation due to the overhead of the pipelining latches for the single-transistor latch is only 4.7%, versus 15% and 22% for the true single-phase latch and the two-phase static flip-flop, respectively.
The single-transistor latch is also very small, which can have a major impact in reducing the area of latch-intensive architectures such as filter structures used in digital signal processing.
The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High.
The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition.
When OE is Low, the latched or transparent data appears at the outputs.
The "D transparentlatch": C is clock input, D is data input, output Q reflects the state, Q follows D when C=1, and Q equals the D value when C was last 1 when C=0.
The 1 bit counter built from a clocked D latch will oscillate at an uncontrolled rate if the time during when C=1 is too long.
Recall of progression from RS latch to transparentlatch to flip-flop and the motivation for the well defined state change point called the clock tick.
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a first transparentlatch which receives the data and is clocked by the input clock;
a second transparentlatch which receives data from the first transparentlatch and is clocked by a delayed output clock, the delayed output clock being a delayed version of the output clock; and
an output latch which receives data from the second transparentlatch and is clocked by the output clock.
