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	Very long instruction word - Wikipedia, the free encyclopedia
		In a VLIW, the compiler predetermines the schedule of operations: while one multiplier is working on the first result, the compiler has scheduled a NOP for the other multiplier, until the result from the first multiply is ready.
		The term VLIW, and the VLIW architecture concept, was invented by Professor Josh Fisher in his research group at Yale University in the early 1980s.
		The VLIW architecture is growing in popularity, particularly in the embedded market, where it is possible to customize a processor for an application in an embedded system-on-a-chip.
	en.wikipedia.org /wiki/VLIW (1318 words)

	VLIW: old architecture of the new generation
		The first VLIW computer Cydrome Cydra-5 used a 256bit instruction and a special mode supporting a sequence of 6 40bit ops, that is why its compilers could generate a mixture of a parallel code and a serial one.
		VLIW processors are an example of the architecture for which the program gives precise data on parallelism - the compiler reveals parallelism in the program and notifies the hardware on which operations do not depend on each other.
		The VLIW architecture is implementation of the conception of the internal parallelism in microprocessors.
	www.digit-life.com /articles2/vliw (6438 words)

	vliw (Site not responding. Last check: 2007-11-06)
		The term VLIW, and the VLIW architecture concept, was by Prof.
		His original development of Trace Scheduling as a compilation technique for VLIW was developed when he was a graduate student at New York University.
		As the number of transistors on a chip has grown, the perceived disadvantages of the VLIW have diminished in importance and the principled architecture is growing in popularly, particularly in the embedded market, where it is possible to customize a processor for an application in an embedded SOC.
	www.yourencyclopedia.net /VLIW.html (1146 words)

	Simulation/evaluation environment for a VLIW processor architecture
		VLIW is not a recent concept; in fact, it originated as an extension of microcode-based techniques [3,4], though the concept has changed drastically since its inception.
		VLIW implementations have been described as "a natural successor to RISC," because complexity is moved from the hardware into the compiler.
		Since a VLIW processor is characterized by having many functional units, the execution of an instruction pair as two separate instructions might not be detrimental as long as the pair is not in the critical path of the program (neglecting penalties arising from having larger code size).
	www.research.ibm.com /journal/rd/413/moreno.html (8020 words)

	VLIW (Site not responding. Last check: 2007-11-06)
		In a VLIW, the compiler predetermines the schedule of operations: While onemultiplier is working on the first result, the compiler has scheduled a NOP for the othermultiplier, until the result from the first multiply is ready.
		His original development of Trace Scheduling as a compilationtechnique for VLIW was developed when he was a graduate student at New York University.
		Prior to VLIW, the notion of prescheduling functional units and instruction levelparallelism in software was well established in the practice of developing horizontal microcode.
	www.therfcc.org /vliw-224056.html (1182 words)

	VLIW History
		But they have continued to refine VLIW technology, and both founders are now bringing their expertise to Hewlett-Packard Labs, which has produced the Playdoh research machine [PDF].
		Thus the re-emergence of VLIW came with a new wave of media processing chips, led by Chromatic's MPact and Philips's TriMedia, which led to the development of the first really publicly successful VLIW implementation: the Texas Instruments C6X series, which is discussed in greater detail in the implementation section of this site.
		In the 1970s, VLIW was nearly un-implementable due to the prohibitively expensive nature of memory at the time.
	www.ecs.umass.edu /ece/koren/architecture/VLIW/1/history.html (391 words)

	VLIW Processors and Trace Scheduling
		VLIW machines (and trace scheduling with them) are on the comeback trail.
		The VLIW approach simplifies the hardware greatly since all the instruction scheduling and register renaming becomes the duty of the compiler.
		VLIWs may be considered a degenerate case of a chunky architecture and as such methods developed for one may be applicable for the other.
	www.cs.utah.edu /~mbinu/coursework/686_vliw/old (4469 words)

	VLIW Difficulties of Implementation
		VLIW has been slow to gain market acceptance due in large part to the human programming difficulties involved.
		VLIW's advantages come largely from having an intelligent compiler that can schedule many instructions simultaneously (in a large word).
		VLIW also has some problems with the inflexibility of its compiler-first design.
	www.ecs.umass.edu /ece/koren/architecture/VLIW/1/difficulties.html (253 words)

	Extending Static Synchronization Beyond SIMD and VLIW (Site not responding. Last check: 2007-11-06)
		VLIW (Very Long Instruction Word) machines are successful in large part because they preserve this property while providing more flexibility in terms of what kinds of operations can be parallelized.
		However, recent developments, such as VLIW (Very Long Instruction Word) computers [Ell85], are not adequately described by classification as SIMD or MIMD.
		The VLIW execution of this code would merely observe that all "inter-process" synchronizations are satisfied by the static timing constraints (i.e., all the arcs point backward in time), and no synchronization cost would ever be incurred.
	dynamo.ecn.purdue.edu /~hankd/CARP/TREE88_25/paper.html (6196 words)

	VLIW - a Whatis.com definition - see also: very long instruction word (Site not responding. Last check: 2007-11-06)
		Very long instruction word (VLIW) describes a computer processing architecture in which a language compiler or pre-processor breaks program instruction down into basic operations that can be performed by the processor in parallel (that is, at the same time).
		VLIW is sometimes viewed as the next step beyond the reduced instruction set computing (RISC) architecture, which also works with a limited set of relatively basic instructions and can usually execute more than one instruction at a time (a characteristic referred to as superscalar).
		The main advantage of VLIW processors is that complexity is moved from the hardware to the software, which means that the hardware can be smaller, cheaper, and require less power to operate.
	whatis.techtarget.com /definition/0,289893,sid9_gci214395,00.html (328 words)

	MacKiDo/Dojo/EPICisRISC
		VLIW (Very-Long Instruction-Word) is a form of RISC, where you can "group" RISC instructions into a bigger "word" -- so big it called a Very-Long Instruction Word -- then it executes all the instructions in parallel.
		Basically, it uses VLIW instructions, but has some "hints" embedded in the instruction set to help with the parallelism and to reduce branching (with predication), and it has a few more registers, and some other minor changes.
		With VLIW if you try to scale it up to read 6 instructions at a time, it is not an even divisor of 4 -- all the old code is designed for groupings of 4.
	www.mackido.com /Hardware/EPICisRISC.html (1555 words)

	Embedded.com - VLIW Architecture Emerges as Embedded Alternative
		The hallmark of VLIW is the ability to extract a highly parallel instruction stream from the applications program with which it is supplied, and dole those machine instructions out to the chip's numerous execution units.
		By definition, the term VLIW refers to a wide-bit-length word into which must be packed-in advance-the different commands, or op-codes, of all the instructions to be executed simultaneously by the VLIW processor on the next clock cycle.
		VLIW detractors have argued that any compiler agile enough to effectively schedule so many simultaneous instructions will be overly complex and difficult to write.
	www.embedded.com /story/OEG20010222S0039 (1891 words)

	ST \| CHALLENGE 1st EDITION 2000 \| All you have to do is dream
		VLIW stands for Very Long Instruction Word and is a type of computer architecture developed to provide very high performance in microprocessors without using complicated hardware instruction scheduling and dispatch, which is the approach used in most modern microprocessors.
		VLIW reverses the trend towards ever more complex architectures by eliminating the hardware required to re-order and schedule instructions while the program is running.
		On the other hand, VLIW compilers are considerably more complex to develop than traditional compilers and the difficulty of writing powerful VLIW compilers is increased by an order of magnitude if they are required to work across a wide variety of hardware architectures.
	www.st.com /stonline/press/magazine/challeng/1stedi00/chal09.htm (1119 words)

	BYTE.com
		In hardware terms a VLIW processor is very simple, consisting of little more than a collection of function units (adders, multipliers, branch units, etc.) connected by a bus, plus some registers and caches.
		A VLIW compiler must have an intimate knowledge of the hardware details of its processor, down to the number of function units and even their individual latencies.
		VLIW arose to meet the needs of scientific number crunching, but it might prove less capable on the sorts of object-oriented and event-driven programs that are more common in the PC community.
	www.byte.com /art/9604/sec8/art3.htm (1795 words)

	Reservoir Labs® -- Multiflow VLIW (Site not responding. Last check: 2007-11-06)
		It was apparent when we started that the architectural principles and compiler techniques that made the Multiflow architecture so compelling in a minisupercomputer product would be even more compelling for single chip computer architectures as VLSI technology permitted the integration of multiple functional units on the same chip.
		The prediction that VLIW architecture would become important in single chip computers has come true: most advanced DSP, media processing, and next generation server processors are based on VLIW architecture and compiler principles.
		The standard issue width in contemporary commercial VLIW processors is only 8 operations, while the Multiflow machine had an instruction issue width of 28 operations.
	www.reservoir.com /vliw.php (716 words)

	Definition of VLIW
		This was partly inspired by the difficulty Josh observed at Yale of compiling for architectures like Floating Point Systems FPS164, which had a complex instruction set architecture that separated instruction initiation from the instructions that saved the result -- leading to the need for very complicated scheduling algorithms.
		Philips' TriMedia processor as well as Intel's Itanium IA-64 processor are examples of VLIW CPUs.
		The VLIW architecture is growing in popularity, particularly in the embedded market, where it is possible to customize a processor for an application in an embedded SOC.
	www.wordiq.com /definition/VLIW (1286 words)

	VLIW at IBM Research
		The VLIW effort at the IBM T.J. Watson Research Center started in 1986, leading to our first publications [1, 2] describing a new approach to exploit instruction-level parallelism in branch-intensive programs.
		This approach is based on expressing a program as a sequence of tree-instructions, each of which contains a multiway branch and multiple operations, all executable concurrently.
		The continuing development of tools and an environment to simulate/evaluate the potential benefits of VLIW technology.
	www.research.ibm.com /vliw (198 words)

	ForthWiki - VLIW (Site not responding. Last check: 2007-11-06)
		Архитектура VLIW известна с начала 80-х в университетских проектах, но только сейчас, с развитием технологии микросхем, она нашла своё достойное воплощение.
		Подавляющее большинство мультимедийных процессоров с производительностью более 1 миллиарда операций/ секунду базируется на VLIW архитектуре.
		Серьёзная проблема VLIW - рост сложности регистрового файла и связей с ним вычислительных устройств.
	wiki.forth.org.ru /VLIW (112 words)

	VLIW
		VLIW architectures are sometimes classified as a type of static superscalar architecture.
		Producing code for VLIW machines is difficult; trace scheduling is a helpful compiler technique.
		The most famous VLIW machine was built by (the late) Multiflow Computer, Inc.
	www.linuxguruz.com /foldoc/foldoc.php?VLIW (135 words)

	mAgic VLIW presented at Stanford conference
		MAgic VLIW surface is about 25 square millimetres, equal to a fourth of a little finger nail, and it is able to do a billion and a half operations per second, spending only half a watt, which means fifty times less than a personal computer with the same computing power.
		MAgic VLIW will be immediately marketed by Atmel with a first System on Chip named "Janus", specialized in synthetic beam-forming of directional waves (audio, radio, ultrasonic and radar) and physical modelling (real-time reproduction of a system behaviour, starting from equations that describe it).
		A second application that mAgic VLIW will enable is a very high quality and a low cost hand-free audio-conference system: you can phone and in the meantime do any other kind of activity (voice will be received through several microphones and it will be separated from echoes and noises).
	www.eurekalert.org /pub_releases/2003-08/indf-pis080103.php (746 words)

	Handling Irregular ILP Within Conventional VLIW Schedulers Using Artificial Resource Constraints
		This presents a significant problem for the compiler, since tradition VLIW compilers work directly with physical resources to determine what can and cannot be scheduled in parallel.
		This enables the use of the large body of work (and software) in VLIW compilation to be directly used for these irregular processors.
		We believe that the development of these ideas opens the door for using classic VLIW compilation methods for irregular embedded VLIW DSPs and is a significant step forward in the development of software tools for embedded processing.
	www.gigascale.org /pubs/89.html (688 words)

	Fujitsu introduces a VLIW based processor (Site not responding. Last check: 2007-11-06)
		VLIW architecture allows the compiler rather than the processor to be responsible for guaranteeing simultaneous issuing of each packet, as opposed to a superscalar processor which has to decide itself whether or not multiple instructions can be executed at the same time.
		Development environments of the new processor core are based on an advanced version of a vector compiler used in Fujitsu supercomputers.
		Packed VLIW instructions can be placed on memory without increasing instruction memory size.
	www.hoise.com /primeur/00/articles/monthly/AE-PR-03-00-49.html (524 words)

	Glossary Search Results
		VLIW uses encoded instructions that are even more complex than the instructions used in CISC.
		While RISC took instruction sets in a simpler direction by making instructions smaller, VLIW moves them in a more complex direction by encoding four or more instructions into a single operation.
		VLIW is used in the Hewlett Packard PA-RISC series of microprocessors, and formed the basis of some of the architecture used in Intel's IA-64 processors.
	www.geek.com /glossary/glossary_search.cgi?Very (281 words)

	DAISY -- Architecture Emulation thru Dynamic Compilation
		The VLIW effort at the IBM T.J. Watson Research Center started in 1986 and has yielded several generations of compilers as well as prototype hardware.
		A variety of VLIW and other novel ILP architectures have been proposed over the years.
		VLIW offers the prospect of high issue rates and a significant advantage in simplicity over out-of-order superscalar implementations.
	www.research.ibm.com /daisy (421 words)

	Results for 'VLIW Microprocessors'
		- vliw: 13, microprocessors: 4, vliw microprocessors: 1
		- vliw: 1, microprocessors: 4, vliw microprocessors: 2
		VLIW core as a successor to the TriMedia TM1000.
	odysseus.ieee.org /ieeesearch/query.html?qt=VLIW+Microprocessors (886 words)

	HP helps put VLIW into STMicro's system-chip
		SAN MATEO, Calif. — The making of STMicroelectronics' ST210 very long instruction word (VLIW) processor is the story of how two companies with similar goals and different strengths came together to tackle some of the most harrowing problems in system-on-chip design.
		In this sense, the ST210 is a much purer form of VLIW as envisioned by the creators of the instruction set and compiler technology.
		Bramley said the VLIW engine is not an end in itself, but will become an integral part of system-on-chip devices for applications that now rely heavily on hardwired circuitry.
	www.embedded.com /shared/printableArticle.jhtml?articleID=9900461 (907 words)

	ElectronicsWeekly.com - IMEC develops VLIW, coarse-grained DSP (Site not responding. Last check: 2007-11-06)
		IMEC has developed a DSP architecture template combining a very long instruction word (VLIW) processor and coarse-grained array, and a prototype C compiler which enables easy programming of the architecture, the Belgian RandD centre said.
		By combining a VLIW DSP with a coarse-grained array, IMEC has developed a power-efficient flexible architecture template and a retargetable compiler for coarse-grained reconfigurable processors, according to the RandD centre.
		This architectural flexibility and C design flow allows a designer to rapidly explore architectural options for an application domain; applications can be programmed completely in C. IMEC currently has a functioning prototype of the retargetable compiler and is conducting ongoing research in benchmarking the architecture in terms of power, performance and area.
	www.electronicsweekly.co.uk /Article5333.htm (288 words)

	Citations: Bulldog: A compiler for VLIW architectures - Ellis (ResearchIndex)
		A first approach is to determine the required data routes during the execution of the scheduling algorithm.
		Using a trace, it is possible to expose available ILP because several basic blocks are included in it, which can be scheduled in parallel on the underlying VLIW processor as a single unit.
		Using a trace, it is possible to expose available ILP because several basic blocks are included in it which can be scheduled in parallel on the underlying VLIW processor.
	citeseer.ist.psu.edu /context/10699/0 (1376 words)

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