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	Very long instruction word - Wikipedia, the free encyclopedia
		In a VLIW, the compiler predetermines the schedule of operations: while one multiplier is working on the first result, the compiler has scheduled a NOP for the other multiplier, until the result from the first multiply is ready.
		The term VLIW, and the VLIW architecture concept, was invented by Professor Josh Fisher in his research group at Yale University in the early 1980s.
		The VLIW architecture is growing in popularity, particularly in the embedded market, where it is possible to customize a processor for an application in an embedded system-on-a-chip.
	en.wikipedia.org /wiki/VLIW (1580 words)

	Talk:Very long instruction word - Wikipedia, the free encyclopedia
		VLIW machines, on the other hand, rely on the compiler to explicitly tell the processor exactly what every functional unit is doing at any instant -- all packed into a single instruction (the Very Long Instruction Word).
		A compiler for a VLIW machine will schedule the instructions for the "true" side of the condition into some of the functional units, and the "false" side of the condition into other functional units, so both sides get executed simultaneously.
		As I previously mentioned, Cydrome was a company pioneering VLIW concepts in the same timeframe as Multiflow, but there's no mention of that in the article.
	en.wikipedia.org /wiki/Talk:Very_long_instruction_word (326 words)

	VLIW - a Whatis.com definition - see also: very long instruction word (Site not responding. Last check: 2007-10-21)
		Very long instruction word (VLIW) describes a computer processing architecture in which a language compiler or pre-processor breaks program instruction down into basic operations that can be performed by the processor in parallel (that is, at the same time).
		VLIW is sometimes viewed as the next step beyond the reduced instruction set computing (RISC) architecture, which also works with a limited set of relatively basic instructions and can usually execute more than one instruction at a time (a characteristic referred to as superscalar).
		The Crusoe family of processors from Transmeta uses very long instruction words that are assembled by a pre-processor that is located in a flash memory chip.
	whatis.techtarget.com /definition/0,,sid9_gci214395,00.html (348 words)

	Nitesh Batra Project
		word is retrieved from memory for processing, the VLIW processor executes the operations in each field in parallel on the various functional units.
		VLIW processors are a class of parallel processors capable of performing several operations per clock cycle.
		Instruction level parallelism occurs when a component of an algorithm can be executed independent of the results of another component of the algorithm.
	www.wam.umd.edu /~nbatra/411proj/vliwopening.htm (640 words)

	MacKiDo/Dojo/EPICisRISC
		VLIW (Very-Long Instruction-Word) is a form of RISC, where you can "group" RISC instructions into a bigger "word" -- so big it called a Very-Long Instruction Word -- then it executes all the instructions in parallel.
		Basically, it uses VLIW instructions, but has some "hints" embedded in the instruction set to help with the parallelism and to reduce branching (with predication), and it has a few more registers, and some other minor changes.
		With VLIW if you try to scale it up to read 6 instructions at a time, it is not an even divisor of 4 -- all the old code is designed for groupings of 4.
	www.mackido.com /Hardware/EPICisRISC.html (1555 words)

	[No title] (Site not responding. Last check: 2007-10-21)
		One of the ways hardware typically deals with the situation is by treating the conflicting instructions as a no-operation (nop) and indicating an error has occurred, or by indicating an error situation exists and assigning priorities to the instructions to control which single instruction wins in writing to the conflicting target register.
		By resolving a write priority conflict on a word basis, it is possible to have half of a double-word operation complete, on the single word portion of the CRF that was not in conflict, while the other conflicting word operation follows the dictates of a hardware priority mechanism.
		It is also possible to have instructions that operate on double-word data (64-bits) or word data (32-bits) mixed in a VLIW with instructions that operate on half-word data (16-bits), such as a half-word load instruction.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=00/79395.020801&ELEMENT_SET=DECL (5986 words)

	[No title]
		A VLIW implementation has capabilities very similar to those of a superscalar processor-issuing and completing more than one operation at a time-with one important exception: the VLIW hardware is not responsible for discovering opportunities to execute multiple operations concurrently.
		Because VLIW instructions explicitly specify several independent operations-that is, they explicitly, specify parallelism-it is not necessary to have decoding and dispatching hardware that tries to reconstruct parallelism from a serial instruction stream.
		The VLIW nature of the horizontal microinstructions is used to attain a high-performance interpretation of the high-level instruction set by executing several low-level steps concurrently.
	carbon.cudenver.edu /csprojects/CSC5551/StudentWeb/Parallel_Architecture_Group/Projects/Ramanujam_Rengarajan/2003_05_04_VLIW_Report_Rajan.doc (4427 words)

	C:\HMPRO2\gifs\micropro.htm
		Their research into VLIW (very long instruction word) technology, which is supported by Altera, ATandT, IBM, Intel Corporation and the National Science Foundation, led to a best paper award for Conte and Sathaye at the International Symposium on Microarchitecture last November.
		Unlike current microprocessors, VLIW has the capability to run the number of instructions in parallel needed to process a command every five- hundred- millionth of a second, but it is not compatible with current software.
		VLIW computers are able to process the information so quickly because the work is done in the compiler, a function in the software that translates a program's high-level computer language into the low-level machine code the computer requires, rather than in an extra piece of hardware.
	www.ncsu.edu /ncsu/univ_relations/releases/micropro.html (793 words)

	[No title]
		Comparison: Microcode is written by machine architects: once for the lifetime of the machine (some machines actually allowed their microcode to be changed) VLIW instructions are written by the compiler 3.
		instructions for a particular pipeline are not in a fixed location e.
		This allows instructions from both the then and else branches of a loop to be executed in parallel.
	www.ugrad.cs.ubc.ca /spider/cs318/notes/4-09-98.txt (777 words)

	[No title] (Site not responding. Last check: 2007-10-21)
		Instruction type and prediction information are built into the instruction cache to speedup the prediction process.
		Decrease the likelihood that an instruction has to wait for the results of previous instructions when it is being considered for execution.
		The positions of the instructions inside the molecule determine which FU while the instruction be routed.
	graphics.cs.ucdavis.edu /~jchen007/UCD/ECS250A/Project.doc (3715 words)

	[No title] (Site not responding. Last check: 2007-10-21)
		The memory is accessed for each instruction fetched and fed directly to the decode logic to control the execution of multiple execution units in parallel.
		The present invention focuses on aspects of VLIW memory address generation units and instructions for use in conjunction therewith that can support different indirect addressing modes for VLIW access providing a programmer with a degree of flexibility in VLIW execution and loading which closely parallels that which is available for data access.
		For the case of a load VLIW (LV) SIW, the direct address in the LV instruction is stored in the register 206, and the VIM address 221 results from selecting register 206 through the multiplexer 208 for each instruction to be loaded into a VLIW in VIM 209 at the address register specified by 206.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=01/04765.010118&ELEMENT_SET=DECL (7369 words)

	Very Long Instruction Word Processors (VLIW) (Site not responding. Last check: 2007-10-21)
		Very long instruction word (VLIW) ideas came from the parallel microcode way back in computing's earliest days and from the first supercomputers such as the Control Data CDC6600 and IBM 360/91.
		The first true VLIW machines were mini supercomputers in the early 1980s from three companies: Multiflow, Culler, and Cydrome.
		Cydrome's pioneering Cydra 5 also used a 256-bit instruction word, with a special mode that executed each instruction as a sequence of six 40-bit operations.
	web.ukonline.co.uk /p.boughton/vliw.htm (321 words)

	An Introduction to Very-Long Instruction Word (VLIW) Computer Architecture from Philips White Papers at ZDNet UK (Site not responding. Last check: 2007-10-21)
		VLIW architectures are distinct from traditional RISC and CISC architectures implemented in current mass-market microprocessors.
		VLIW microprocessors and superscalar implementations of traditional instruction sets share some characteristics—multiple execution units and the ability to execute multiple operations simultaneously.
		The techniques used to achieve high performance, however, are very different because the parallelism is explicit in VLIW instructions but must be discovered by hardware at run time by superscalar processors.
	whitepapers.zdnet.co.uk /0,39025945,60012157p-39000401q,00.htm (150 words)

	Object code compatible representation of very long instruction word programs (US5669001) (Site not responding. Last check: 2007-10-21)
		In this way, programs are represented in main memory in an implementation independent manner (i.e., without reflecting the organization of the processor where they are executed), the implementation-specific aspects are introduced as part of the instruction cache reload/fetch processes, and the simplicity in instruction dispatch logic that is characteristic of VLIW processors is preserved.
		The resulting VLIWs can be executed starting from any operation within them (e.g., branching into them is possible), and there is a one-to-one correspondence among primitive operations in main memory and in the I-cache.
		Moreover, a framework is provided for generating (compiling) code which exploits the parallel execution features of a VLIW processor (parallelized code) which is also executable by a sequential processor without unduly affecting performance.
	www.delphion.com /details?&pn=US05669001__ (525 words)

	VLIW - Very Long Instruction Word
		Very Long Instruction Word, instruction sets with large-sized complex instructions encoded into one instruction.
		The VLIW architecture is capable of executing many operations in a single-clock cycle and has become the architecture of choice for high-performance processors.
		VLIW also provides simple cost-effective control of parallelism and can scale to support architectural enhancements.
	www.auditmypc.com /acronym/VLIW.asp (164 words)

	HP sued over very long instruction word (VLIW) technology
		A FIRM IS TAKING legal action against Hewlett Packard over very long instruction word (VLIW) programming in a move which may also have implications for the Intel Itanium processor, which uses elements of VLIW developed by HP.
		VLIW Technology LLC, according to reports, wants HP to stop distributing VLIW (very long instruction word) technology to others after it allegedly licensed the design in 1990.
		ST and HP signed a deal to develop customisable VLIW cores in 1999, as this release explains.
	www.theinquirer.net /?article=6734 (243 words)

	VLIW Microprocessors - Computerworld
		Variable-length instructions are more difficult for a chip to process, though, and the longer CISC instructions are especially complex.
		Because they have to deal with fewer types of instructions, RISC chips require fewer transistors than comparable CISC chips and generally deliver higher performance at similar clock speeds, even though they may have to execute more of their shorter instructions to accomplish a given function.
		VLIW chips don't need most of the complex control circuitry that superscalar chips must use to coordinate parallel execution at runtime.
	www.computerworld.com /printthis/2000/0,4814,43018,00.html (758 words)

	Very Long Instruction Word from FOLDOC (Site not responding. Last check: 2007-10-21)
		A horizontally encoded instruction word which encodes four or more operations might be considered "very long".
		VLIW architectures are sometimes classified as a type of static superscalar architecture.
		They are static in the sense that which units operate in parallel is determined by the instruction rather than by dynamic scheduling at run-time.
	www.instantweb.com /d/dictionary/foldoc.cgi?VLIW (123 words)

	Body
		Instructions are issued in-order through a FIFO queue to maintain correct data flow.
		All instructions pass through the issue stage in order, but instructions stalling on operands can be bypass by later instructions whose operands are available.
		RAW hazards are handled by delaying instructions in reservation stations until all their operands are available.
	www.cs.uni.edu /~fienup/cs240f03/lectures/lec29_12-2-03.htm (681 words)

	EDN: VLIW compiler to take i860 'hyperscalar.' (very long instruction word microprogramming to be used in Intel's ... (Site not responding. Last check: 2007-10-21)
		EDN: VLIW compiler to take i860 'hyperscalar.' (very long instruction word microprogramming to be used in Intel's upcoming 80860 RISC chip)@ HighBeam Research
		VLIW compiler to take i860 'hyperscalar.' (very long instruction word microprogramming to be used in Intel's upcoming 80860 RISC chip)
		The technology, developed by Multiflow Computer Inc, overlaps instruction execution in very long instruction word (VLIW) compilation and schedules data precedence at compile time.
	www.highbeam.com /library/doc0.asp?DOCID=1G1:8241180&refid=holomed_1 (233 words)

	HP Fellows: Josh Fisher biography
		Josh Fisher is an industry pioneer in Very Long Instruction Word (VLIW) computing -- a CPU architecture that reads a group of instructions and executes them all at the same time, making for faster processing.
		He came to HP in 1990, attracted by the opportunity to work on the PA-WW (Precision Architecture--Wide-Word) project, which is heavily based on VLIW and eventually became IA-64.
		Very Long Instruction Word architectures and compiling, custom-fit processors.
	www.hpl.hp.com /about/honors/HPfellows/fisher.html (233 words)

	Object-code compatible representation of very long instruction word programs (US5951674)
		In this way, programs are represented in main memory in an implementation-independent manner, the implementation-specific aspects are introduced as part of the instruction cache reload/fetch processes, and the simplicity in instruction dispatch logic that is characteristic of VLIW processors is preserved.
		Also provided is a mechanism and an apparatus for the interpretation of tree-instructions by a computer system based on a VLIW processor.
		Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
	www.delphion.com /details?&pn=US05951674__ (464 words)

	22C:122/55:132, Lecture 21, Spring 2001
		Each instruction may also perform a memory operation, loading or storing the contents of register R in a memory loaction computed by adding the contents of register X to the displacement DISP.
		This instruction set also assumes that every instruction will be a memory reference instruction, although it is likely that there will be no-op opcodes in each functional unit's field of the instruction word.
		With a VLIW architecture, their presence is exposed, so their number must be fixed for all implementations of the architecture.
	www.cs.uiowa.edu /~jones/arch/spring01/notes/21.html (1417 words)

	VLIW definition - isp.webopedia.com - The Glossary for Internet Service Providers
		A chip with VLIW technology is capable of executing many operations within one clock cycle.
		Essentially, a compiler reduces program instructions into basic operations that the processor can perform simultaneously.
		The operations are put into a very long instruction word that the processor then takes apart and passes the operations off to the appropriate devices.
	isp.webopedia.com /TERM/V/VLIW.html (100 words)

	EETimes.com - IMEC rethinks configurability (Site not responding. Last check: 2007-10-21)
		San Francisco — The IMEC research center is blending concepts in very long instruction word processing with emerging ideas in reconfigurable computing arrays to form a processing cluster that is at once powerful, configurable and low enough in power for use in mobile applications.
		In IMEC's novel, hybrid architecture, each of the functional units of a relatively conventional very long instruction word (VLIW) processor becomes, in effect, an element in the top row of a heterogeneous array of processing elements.
		In the process of analyzing an algorithm, the design team creates an instance of the template in which the instruction set of the VLIW machine, the number and the operation of its function units, and the function and interconnect topology of the coarse-grained processing array are all determined from the application requirements.
	www.eetimes.com /showArticle.jhtml?articleID=18700532 (1332 words)

	The hidden currents powering Intel's next gen chips
		Then there is the x86 instruction decoder which on simple processors takes up a significant amount of room and of course consumes power.
		That company was Transmeta and its line of processors weren’t x86 at all, they were VLIW (Very Long Instruction Word) processors which used "code morphing" software to translate the x86 instructions into their own VLIW instruction set.
		Intel can make a VLIW processor with a large number of small, low power cores and devote one or more of these to translating x86 to the VLIW ISA, they will partly hold the translation software in the bigger cache so it’ll rarely need to hit RAM.
	www.theinquirer.net /?article=25496 (2030 words)

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