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Topic: Visual Instruction Set

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	Great Microprocessors of the Past and Present (V 13.4.0)
		Instructions are predecoded in cache, incorporating some ideas from dataflow designs - source operands are replaced with references to the instructions which produce the data, rather than matching up an instructions source registers with destination registers of earlier instructions during result forwarding in the execution stage.
		It was a huge (at the time) 450,000 transistor chip with a stack based instruction set, described as "essentially a gigantic microcode ROM with a simple 32 bit data path bolted to its side".
		The C100 was a three-chip set like the Motorola 88000 (but predating it by two years), with a Harvard architecture CPU and separate MMU/cache chips for instruction and data.
	www.cpushack.net /CPU/cpu4.html (6954 words)

	SPARC Behavior and Implementation
		The additional instructions, known as the Visual Instruction Set or VIS, are rarely generated automatically by the compilers, but they may be used in assembly code.
		If the instruction is a floating-point compare, the kernel updates the condition codes to reflect the result; if the instruction is an arithmetic operation, it delivers the appropriate result to the destination register.
		The kernel software that is used to emulate trapped floating-point instructions, however, does not implement nonstandard mode, in part because the effect of this mode is undefined and implementation-dependent and because the added cost of handling gradual underflow is negligible compared to the cost of emulating a floating-point operation in software.
	docs.sun.com /source/806-3568/ncg_sparc.html (2663 words)

	Concrete Programming Paradigm for Kinetic Typography
		The visual instruction set consists of typographic operators such as color, alignment, and size, enabling the user to create free-form designs of kinetic typography.
		The visual nature of the system is inspired by a spatially structured type of poetry known as ``concrete poetry,''[1] where the arrangement of words take on form.
		We introduce several innovations to visual programming systems that gain from a primarily aesthetics-centered approach, such as the use of a freely expandable space and the introduction of clustering structures inspired by concrete poetry.
	acg.media.mit.edu /projects/kinetext/vl97.html (1272 words)

	System and method for routing operands within partitions of a source register to partitions within a destination ... (Site not responding. Last check: 2007-11-03)
		Instructions fetched from instruction cache 112 are transferred to decode unit 114 which decodes the instructions to determine the operands used by the instruction as well as to bit-encode the instruction for the execution units of vector ALU 116 and integer ALU 118.
		Instruction albl is shown to cause movement of sub-slot data in accordance with reference numeral 144, while operation blal causes movement of sub-slot data in accordance with reference numeral 146.
		Instruction albl serves to concatenate the lower half sub-slots of the source registers as opposed to concatenating the upper half sub-slots resulting from instruction ahbh.
	www.freepatentsonline.com /5893145.html (18981 words)

	MMX
		It's a two-step process: in phase 1 the Unpack instruction is used to interleave the word (16-bit) elements of adjacent rows, and in phase 2 the results of the first phase are unpacked again, this time using doubleword (32-bit) Unpack instructions to create the desired outputs.
		If it's not possible to issue two instructions (for instance, if the second instruction requires the result of the first), the first instruction is issued to the first pipe and nothing is issued to the second pipe.
		The instruction decoder was redesigned to quadruple the throughput of MMX instructions, allowing it to decode two MMX instructions per cycle.
	web.cs.wpi.edu /~matt/courses/cs563/talks/powwie/p3/mmx.htm (5050 words)

	Linux.com - Linux Parallel Processing HOWTO: SIMD Within A Register (e.g., using MMX)
		This approach can yield the highest performance, but it requires a change to the processor's instruction set and generally places many restrictions on field size (e.g., 8-bit fields might be supported, but not 12-bit fields).
		The answer is that you use a series of ordinary instructions to perform the operation with carry/borrow across fields, and then correct for the undesired field interactions.
		instruction is really misnamed; not only can it perform an arbitrary permutation of the fields, but it also allows repetition.
	www.linux.com /howtos/Parallel-Processing-HOWTO-4.shtml (2911 words)

	RISC for Graphics: A Survey and Analysis of Multimedia Extended Instruction Set Architectures
		Using the select field of the instruction, a single subword is selected from the second source register and is used as a scalar in the operation on the vector.
		Regardless of whether the programmer chooses to call assembly instructions directly or call them from C macros, he or she must be prepared for a significant amount of additional coding effort.
		A single unpacking instruction was required at the end of the unrolled loop in Box 1, hence preventing the reduction from being an ideal 50%.
	www.tc.umn.edu /~erick205/Papers/EE8362/8362Paper.html (5232 words)

	Great Microprocessors of the Past and Present (Site not responding. Last check: 2007-11-03)
		Instructions were always fetched two at a time from the instruction cache which partially decoded the instruction pairs and set a bit to indicate whether they were dependent or could be issued simultaneously (effectively generating two-word VLIWs in the cache from an external stream of instructions).
		IBM had been developing hardware to translate Pentium instructions for the PowerPC in a similar manner as part of the PowerPC 615 CPU (able to switch between instruction 80x86, 32-bit and 64-bit PowerPC instruction sets in five cycles (to drain the execution pipeline)), but the project was killed after significant development for marketing reasons.
		Most instructions are predicated, a design very similar to the TI 320C6x DSP, but with 128 general 64-bit and 128 floating point registers, and 64 predicate bits (a type of condition code).
	bwrc.eecs.berkeley.edu /CIC/archive/cpu_history.html (15782 words)

	Visual Instruction Set : VIS (Site not responding. Last check: 2007-11-03)
		terms defined : Visual Instruction Set : VIS
		VIS includes a number of operations primarily for graphics support, but has more of them than other integer-only SIMD sets.
		If each man were to lay down his weapon, and say, A king and his minions are really so few.
	www.termsdefined.net /vi/vis.html (391 words)

	VIS Instruction Set
		The VIS Instruction Set is a set of RISC instructions which are extensions to the SPARC V9 open processor architecture and are designed to accelerate applications where multiple data entries require the same instruction, such as multimedia, image processing and networking applications.
		The VIS instruction set is a set of high performance SIMD instructions which are supported on all UltraSPARC processors.
		The VIS Instruction Set is designed to accelerate processing of some algorithms by as much as 7 times, by performing up to 10 operations in parallel per cycle.
	www.sun.com /processors/vis (263 words)

	Visual Instruction Set : VIS
		Visual Instruction Set (or VIS) is a SIMD instruction set used on the SPARC series of CPUs, implented only on the 64-bit UltraSPARC processors.
		This can have a negative performance impact on the system when code attempts to run FPU and VIS instructions in succession, causing the registers to have to be re-loaded.
		In this respect VIS is something of an "old" design like MMX, unlike more modern SIMD architechtures like AltiVec.
	www.fastload.org /vi/VIS.html (172 words)

	PS Action Set 1 - David Lloyd
		The first set of Actions for Photoshop presented in this series, are relatively basic, however, they are fundamental to the creation of visual variety and impact for a series of, or an individual image, which you will present to your clients.
		To keep the instruction set for these Actions compact, some general knowledge of Photoshop will be needed.
		Click on the small double rectangle on the tool bar (background-foreground color) Now, with a small soft round brush set for 100% opacity, paint around the details of the area to be in color, basically triming the edges so that the Sepia layer mask is not overlaping past the area of color details.
	homepage.mac.com /david.lloyd/dl_actions/atn_set_pg1.html (1173 words)

	Building 64-Bit Windows Device Drivers, Part II
		While each architecture is slightly different (some use 48 bits, some 64 bits), Visual SoftICE provides a consistent display of data, and allows the user to format the 16 characters in 64-bit addresses as they see fit.
		In the past, processor manufacturers have documented one set of names for registers, while operating system vendors may have had different titles.
		Visual SoftICE attempts to abstract this, by the IT command (also known as the IDT command), for all supported 32 and 64-bit platforms.
	www.devx.com /amd/Article/17086 (1016 words)

	BYTE.com
		MMX instructions use only the 64-bit mantissa portion of the 80-bit FP registers, ign oring the 16-bit exponent portion.
		MMX instructions can pack several data types into these 64-bit regis ters: packed bytes (eight per register), packed words (four per register), packed doublewords (two per register), and a quadword (one 64-bit value per register).
		The MMX instructions are similar to those in Sun's Visual Instruction Set (VIS) for the UltraSparc.
	www.byte.com /art/9610/sec6/art3.htm (726 words)

	Driver Development FAQs
		Although the PCI nexus driver sets these modes by default, the device driver must agree to these settings and if not, it should set proper operation modes.
		Yes, they used to be implemented as nexus drivers, but a set of interfaces were added to the DDI/DKI in Solaris 2.4 to hide many of the changing details of nexus drivers from HBA drivers.
		Applications can express an interest in a set of file descriptors and be notified by the driver that something has changed.
	developers.sun.com /solaris/developer/support/driver/faqs.html (9909 words)

	Get CPU features
		SWAR detection is done once during ggInit(3) and the value is cached for future use, thus it should be fast enough to choose implementations on the fly.
		Note at this stage of development some of these SIMD sets are not yet detected correctly.
		It may also be used if a multiproccesor machine mis-detects the usable SWAR instruction set because the processors are not identical.
	www.ibiblio.org /ggicore/documentation/libgg/1.0.x/ggGetSwarType.3.html (477 words)

	Linux and UNIX as command
		This option instructs the assembler to accept instructions defined in the SPARC-V8 architecture, less the quad-precision floating-point instructions and less the fsmuld instruction.
		This option instructs the assembler to accept instructions defined in the SPARC-V9 architecture, less the quad-precision floating-point instructions, plus the instructions in the Visual Instruction Set (VIS).
		This option limits the instruction set to the SPARC-V9 architecture, adding the Visual Instruction Set (VIS) and extensions specific to UltraSPARC processors.
	www.computerhope.com /unix/uas.htm (874 words)

	Next-generation UltraSPARC-II coming soon - SunWorld - November 1995
		For instance, the first instruction can have four 16-bit addition processes, the second can have four 16-bit multiplication processes, and the third and fourth instructions can consist of either a load, store, or integer.
		The VIS array instruction reduces memory latency by eliminating the need to go to main memory.
		Dedicating a chip to multimedia is very expensive, and even more costly when the standards change and the chip must be replaced, he explained.
	sunsite.uakom.sk /sunworldonline/swol-11-1995/swol-11-micro.html (1260 words)

	Olympus MIC-D: Integrated Circuit Gallery - Sun UltraSPARC Microprocessor
		The processor is also able to dispatch six instructions, rather than four, to the functional units in a fourteen-stage pipeline.
		The specialized pixel operations (Visual Instruction Set or VIS) of the UltraSPARC can operate in parallel on 8, 16, or 32-bit integer values packed into a 64-bit floating-point register.
		More advanced than other competing graphics instruction sets, such as the Intel MMX instructions, Hewlett-Packard PA-RISC MAX, and Motorola 88110 graphics extensions, VIS also features dimensional conversion, edge processing, pattern matching, and pixel distance calculations for MPEG encoders.
	www.olympusmicro.com /micd/galleries/chips/sunultrasparkhigh.html (339 words)

	[No title]
		VIS treats a 64-bit register as 2, 4, or 8 partitioned data words, and performs operations on multiple words with a single instruction.
		We find that loop unrolling as a means for memory latency hiding and increased instruction-level parallelism provides excellent results in both kernels, and that the use of VIS and software prefetching can result in excellent performance gains.
		However, prefetch instructions are not automatically generated, and low-level programming with VIS or prefetch instructions can be difficult and time consuming.
	www.ece.utexas.edu /~allen/Asilomar99/submission.txt (1053 words)

	BYTE.com
		This operation, accomplished with a single UltraSparc instruction, typically requires 24 instructions, according to Sun.
		Other specialized one-cycle instructions support such operations as conversion instructions for packing and expanding pixel data, arithmetic instructions for manipulating large graphics images, and fixed-point compare instructions for examining the z-buffer during 3-D rendering.
		The UltraSparc uses two sets of registers to process graphical commands: The integer registers crunch address calculations for the image data, while the floating-point registers handle manipulation of the image data.
	www.byte.com /art/9601/sec11/art9.htm (1139 words)

	UC Berkeley Multimedia and Graphics Seminar: R. Yung (11/20/96) (Site not responding. Last check: 2007-11-03)
		UltraSPARC-I (Spitfire) is the first microprocessor from SUN that implements the Visual Instruction Set Extension to the 64-bit SPARC version 9 instruction set architecture.
		VIS comprises of instructions that accelerates 2D/3D synthetic graphics, image processing and multi-media applications.
		In this talk, the VIS data types and instruction set will be presented.
	bmrc.berkeley.edu /courseware/cs298/fall96/w13.html (90 words)

	Microprocessor Watch #60; 9/7/2000
		Improved processing performance stems from a high maximum clock rate (800MHz); an enhanced ARM V5TE instruction set; larger caches; a branch-target buffer that provides dynamic branch prediction; and additional SIMD instruction enhancements.
		Intel has added these instructions through ARM's coprocessor mechanism, but actual implementation is part of the processor core.
		The integrated processor incorporates an execution unit based on Sun's SPARC V9 architecture, with a floating-point unit and VIS (visual instruction set) multimedia extensions; independent 16K instruction and data caches; a unified, four-way set-associative 256K L2 cache; a 32-bit 66MHz PCI bus controller; and a PC-100 SDRAM controller with ECC.
	www.mdronline.com /publications/mpw/issues/mpw060.html (556 words)

	[No title]
		We have the architectural expertise and technology to design radically new microprocessors, to craft new and sophisticated ISAs (Instruction Set Architectures).
		These extensions use the floating-point registers (or registers that use that address space) and extend the Floating-Point Unit to do specialized graphics and math processing.
		Typical DSP applications iterate a series and find some cumulative result (SUM Xi*Yj for i, j) This approach is very useful for digitally processing analog signals and array/matrix processing.
	www.redhat.com /support/wpapers/cygnus/cygnus_evaluate (514 words)

	[No title]
		Recently, special purpose multimedia instruction sets have allowed software-only real time video without extra hardware.
		Examples include Hewlett Packard's MAX instruction set, Sun's VIS (Visual Instruction Set), and Intel's MMX instructions.
		Finally, we show how the stream cache motivates a technique for inserting software prefetch instructions that can improve performance with little or no extra hardware cost.
	mambo.ucsc.edu /psl/cis_seminars/199611/19961108.html (740 words)

	docs.sun.com: man pages section 1: User Commands (Site not responding. Last check: 2007-11-03)
		Use of this option to assemble handwritten assembly language is not recommended.
		This option enables the assembler to accept instructions defined in the SPARC-V9 architecture, plus the instructions in the Visual Instruction Set (VIS), with UltraSPARC-III extensions.
		This option enables the assembler to accept instructions defined in the SPARC-V9 architecture, plus the Visual Instruction Set (VIS), with UltraSPARC-III extensions.
	docs.sun.com /app/docs/doc/816-5165/6mbb0m9bi?a=view (848 words)

	SunWorld Online - November - News
		The pipeline can simultaneously process four instructions per cycle even with conditional branches and cache misses.
		Integrated new media support facilitates desktop videoconferencing, real-time MPEG-2 decoding, video effects, texture-mapping, and triangle rendering.
		He said he believes others will follow when they realize the benefits and cost savings involved with embedded new-media processing.
	sunsite.cs.msu.su /sunworldonline/swol-11-1995/swol-11-micro.html (1251 words)

	VIS - Video Information System, Viewable Image Size, Visual Instruction Set, Voice Information System, Volumetric ...
		VIS - Video Information System, Viewable Image Size, Visual Instruction Set, Voice Information System, Volumetric Imaging System
		* Video Information System, Viewable Image Size, Visual Instruction Set, Voice Information System, Volumetric Imaging System
		3) VIS is also derived from Visual Instruction Set
	www.auditmypc.com /acronym/VIS.asp (254 words)

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