
	Where results make sense

Topic: Wafer testing

Related Topics

LRA

PIN

Tamil people

Pedra Branca

Singapore

Moyle

Srivijaya

Seychelles rupee

CAE

Chu Sang Mi

Aurora

Gwelo

974

In the News (Tue 22 Dec 09)

Northern Trust

Marvin Harrison

Peter Chernin

Gary Locke

Match Play

Penelope Cruz

Mickey Rourke

AR Rahman

Danny Boyle

Hugh Jackman

	Integra Technologies: Semiconductor Electrical Testing Services, Wafer Probe & Sort
		We provide full test engineering development service, IC qualification, reliability analysis, tape & reel and technology transfer.
		HTOL, LTOL, HAST, T/C, THB testing, IR Pre-Conditioning, Latch-Up and ESD testing
		For more information on our semiconductor test services, please contact an Integra Sales Office or fill out a Request for Additional Information.
	www.integra-tech.com /services/Semiconductor_Test.htm (303 words)

	/* Rambling comments... */: Wafer thin testing?
		The granularity of the first tests was too great to be able to move quickly; so once they were in place the first thing to do was to break out the lower level code that we wanted to test and use the initial tests to make sure we hadn't changed any behaviour.
		Most of this was done using pair-programming; one of us to introduce tests to the code as quickly as possible and one who knew the existing code and knew how the system hung together.
		The next step is to fill out the tests and refactor the code as required to remove some of the 'fluff', make the code simpler and easier to understand.
	www.lenholgate.com /archives/000299.html (455 words)

	wafer probe testing of wafers - 100% probing of wafer and die products - we test to recognised standards or customer ...
		Wafers are traditionally received from the manufacturers fab pre-probed to a basic level, the majority of the time this comprises of a DC test at room temperature to guarantee that the parts meet the basic parameters according to the manufacturer’s spec.
		If a customer wishes to receive product in wafer form they may wish for die which don't pass to their set specification to be marked with an ink dot so that their own equipment can clearly recognise the rejects when the wafer is processed in house.
		After the test completes the probes then lift, if the die is reject it is marked with an ink dot in the centre and the wafer is then moved into position for the next die, by this method each die on the wafer is probed.
	www.ditech.co.uk /productsandservices/probing.htm (683 words)

	Wafer testing - Wikipedia, the free encyclopedia
		Wafer testing is a step performed during semiconductor device fabrication.
		During this step, performed before a wafer is sent to die preparation, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them.
		The wafer testing is performed by a piece of test equipment called a prober, and the process is sometimes referred to as a probe test or wafer sort.
	en.wikipedia.org /wiki/Wafer_testing (375 words)

	United States Patent: 6,379,982 (Site not responding. Last check: )
		The device wafer includes a plurality of unsingulated semiconductor dies having a plurality of die bond pads being respectively bonded to a plurality of electrically conductive die bond pad connect elements provided on a first surface of the support wafer.
		Upon the unsingulated dies having been burned-in and tested, the wafer is forwarded on for further processing including singulation of the dies with the resilient contact structures being available for permanently connecting the dies to higher level circuits, such as a circuit board.
		The test connection/mounting elements, which preferably are menisci formed by the conductive filling material, or solder, previously disposed in the vias, or feed-throughs, to form globules, such solderballs or bumps, are bonded to mounting pads, or other suitable surfaces, correspondingly positioned and arranged to accommodate the test connection/mounting elements.
	web.engr.oregonstate.edu /~flf/6379982.html (6873 words)

	Wafer level integration and testing - Patent 5366906
		In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in.
		Wafer 10 assembly, with dielectric layer 18 and the fully resisted metal, may now be HDI laser exposed by the adaptive lithography system as is shown in commonly assigned U.S. Pat.
		Temporary "test only" layers may be used to partition the wafer for ease of test, or test layers may interconnect certain aspects of the wafer in a test configuration.
	freepatentsonline.com /5366906.html (8235 words)

	Testing method detecting localized failure on a semiconductor wafer invention
		A determination of whether or not the wafer is defective is made in relation to a spatially related group of filtered failed semiconductor chips on the wafer, where the spatially related group corresponds to a localized failure on the wafer and is used to calculate a defect index value.
		Where an individual wafer within a lot is determined to be defective (e.g., it exhibits an unacceptably low yield), it may be removed from the fabrication process and subjected to a detailed failure analysis.
		On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure.
	www.freshpatents.com /Testing-method-detecting-localized-failure-on-a-semiconductor-wafer-dt20070215ptan20070035322.php (1650 words)

	Semiconductor wafer and testing method therefor invention
		Circuits under electrode terminals and a nonconductor layer of the electrode terminals in semiconductor devices are prevented from being damaged during a test, such as a burn-in test, on the semiconductor devices formed on a wafer.
		[0001] The present invention relates to a semiconductor wafer and a testing method therefore, and in particular to a semiconductor wafer having alignment patterns for conducting tests on the semiconductor wafer and a testing method conducting tests on the semiconductor wafer.
		A number of semiconductor devices are formed on the semiconductor wafer and alignment patterns used in conducting a test of the wafer are provided on the wafer.
	www.freshpatents.com /Semiconductor-wafer-and-testing-method-therefor-dt20060518ptan20060103408.php (1638 words)

	Enviromental Testing Information \| Wafer burn-in system
		With wafer burn-in, special burn-in circuits are built into the wafer to resolve these problems, and burn-in time can be reduced by efficiently driving these special circuits.
		Special burn-in circuits inside the wafer are required to apply efficient stress to the cell and to apply effective stress voltage to peripheral circuits.
		Connections for the test heads and multi-probe cards are made through insert ring pogo pins, providing a design in which reliable connections are made even with test heads opening and closing.
	www.espec.co.jp /english/tech-info/seminar/tw-1/detail_tw-1.html (1064 words)

	Advanced Scientific Concepts Inc \| Wafer Level Testing
		These wafers are then screened and tested for wafer die functionality and operability.
		Wafer testing is the first level of screening in the sequence of many to insure a viable working sensor.
		Each and every readout die on the wafer is tested and graded for the next stage of assembly.
	www.advancedscientificconcepts.com /custom3.html (230 words)

	Wafer-Level Test and Burn-in (WLTBI) - Page 1 of 3
		Conventional electrical testing uses expensive automated test equipment (ATE) on the test floor while conventional burn-in requires burn-in ovens that are kept in their own burn-in areas due to the large amounts of heat that they radiate.
		Both electrical testing and burn-in need a means of supplying the devices under test (DUT) with electrical bias and excitation, whether it's done at wafer level or at package level.
		During electrical testing of individual IC's, electrical bias and excitation are provided by the ATE to the DUT by mechanically contacting its leads.
	www.siliconfareast.com /wl_test_bi.htm (560 words)

	memppa
		In the manufacturing process, after a wafer is fabricated the common practice is to test each IC by positioning a test head containing probes over each IC one at a time to contact the IC's pads, exercise the IC to determine whether it is good, and mark the bad ones.
		During wafer testing the internal processor allows the memory to be tested at full speed and substantially simultaneously with the testing of other memories on the wafer.
		During wafer testing the internal processor system allows the memory to be tested at full speed and substantially simultaneously with the testing of other memories on the wafer.
	www.jmargolin.com /todo/mempap.htm (3551 words)

	Full Wafer Probe Stations - Lake Shore Cryotronics, Inc.
		The stages for the Full Wafer Probe Systems have a travel of 125 mm in the axis of the bellows (X-axis), 51 mm horizontally (Y-axis), and 16 mm to lift and lower the probe (Z-axis).
		The Wafer Stage is also manipulated by 52 mm in both an X and Y axis for reaching any position on a 4" wafer with all probes.
		The optics can be manipulated to view any part of a 2-inch wafer, and in addition, can be retracted and swung away to allow access to the top of the vacuum shroud.
	www.lakeshore.com /desertcryo/probestations/fullwafer.html (1142 words)

	FormFactor at top of its game: Firm earns Smithsonian status for its wafer testing technology
		FormFactor invented a MEMS-based wafer probe card, which is used by semiconductor chipmakers to test silicon wafers for their electrical circuitry performance.
		Wafer testing is a critical and often repeated step along the many highly sensitive processes that go into making semiconductor chips.
		Because FormFactor's technology does this testing or probing when the chips are still in wafer stage and not yet separated and packaged into individual chips, it has driven down the cost of making chips and driven up the yield of good chips that come out of a wafer supply.
	www.contracostatimes.com /mld/cctimes/16881867.htm?template=contentModules/printstory.jsp (1258 words)

	Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (Site not responding. Last check: )
		The equipment includes (1) test sets that are basically extended versions of commercial network analyzers that, heretofore, have been functional up to 110 GHz; (2) recently developed millimeter-wavelength-signal probes that make it possible to take accurate on-wafer measurements; and (3) an amplifier-based solid-state noise source.
		In contrast, by enabling accurate on-wafer measurements, the recently developed signal probes included in the present test equipment can be expected to foster commercialization by making it possible to characterize circuits accurately, in rapid succession, at relatively low cost.
		In tests of a receiver circuit, it was found to be cumbersome to perform noise measurements by use of alternate hot and cold loads in front of a feed horn attached to a wafer probe.
	www.nasatech.com /Briefs/Nov01/NPO20760.html (712 words)

	Wafer Testing
		From a test standpoint, this means lower applied stress voltages in Time Dependent Dielectric Breakdown (TDDB) measurements, lower stimulus levels for capacitance, and smaller voltage steps for IV curves.
		PureLine supports a broad range of on-wafer test processes, from process development through characterization and modeling to long term reliability and failure analysis.
		Cascade Microtech develops advanced wafer probing solutions for the precise electrical measurement and test of integrated circuits (ICs).
	www.yenra.net /silicon-wafers (236 words)

	GSF - Eles Semiconductor Equipment - Final Test and Wafer Level Testing Solutions
		Extensive knowledge and expertise in reliability testing allow ELES to support customers with highly qualified engineering services focusing on the definition, standardization and upgrade of the application process according to the customer's testing needs.
		ELES has gone beyond technologies to approach and solve real testing challenges with the aim to optimise the semiconductor manufacturing process and fill the gap between abstract design and real silicon by delivering products and services that reduce the overall cost of ownership while maximising process flexibility, enhancing yield and improving time-to-market.
		ART200 is an innovative, flexible and universally applicable testing platform that allows design and test engineers to easily and cost-effectively perform debugging, characterization and functional testing on SOC, memory, mixed-signal, analogue and digital devices.
	www.semiconductor-technology.com /contractors/test/eles (705 words)

	Equipment for On-Wafer Testing From 220 to 325 GHz NASA Tech Briefs - Find Articles (Site not responding. Last check: )
		On-wafer vector network analysis of semiconductors is extended to higher frequencies.
		On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an onwafer calibration substrate designed for use with these probes.
		The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz.
	findarticles.com /p/articles/mi_qa3957/is_200601/ai_n17172102 (353 words)

	wafer prober, wafer probing equipment, surplus wafer inspection, Electroglas, and test systems, for sale.
		- Hot Cold stage -65c to +150c, is capable of precise, and thorough environmental test of wafers.
		quick movement from one test area to another, with excellent positioning resolution accuracy.
		www.wafer-probing.com wafer probe, wafer probing, wafer test, wafer inspection, wafer testing.
	www.wafer-probing.com (251 words)

	Applied Precision, LLC - Semiconductor - Probing Process Analysis - waferWoRx
		Accurately probing the wafer and hitting the center of the pad is critical to the probing process and ultimately your bottom line.
		The wafer testing process operates as a fine-tuned system only when a robust sampling and testing methodology is applied to qualify, optimize and monitor each variable.
		As the prober stage moves in the X-axis, a Y-positioning error is caused by errors in wafer alignment and stage orthogonality.
	www.api.com /semi/waferworx.html (791 words)

	Wafer Foundry : FUJITSU
		Fujitsu has offered wafer foundry services since the 1980s, through which it has delivered original LSI technologies to numerous customers.
		, a multi-project wafer testing system, as well as a manufacturing information service that provides timely information from fabrication facilities to customers.
		A means of manufacturing multiple types of IC on the same wafer by mounting multiple types of IC on a single mask.
	www.fujitsu.com /global/services/microelectronics/product/foundry (150 words)

	Wafer Testing (Site not responding. Last check: )
		Certain product families require wafers to be 100% tested before the sawing process.
		This "on-wafer" test allows device characterization and assurance of known good die (KGD) for higher integration level products and die sales.
		Wafer tests are cataloged on a UNIX database, and are available over a wide-area network (WAN) for statistical analysis and automated binning.
	www.macom.com /fabtour/wafertest.htm (84 words)

	EETimes.com - Power semi testing goes wafer scale (Site not responding. Last check: )
		The Tesla probe station allows power semiconductors to be safely tested on the wafer, before the wafer is diced and the chips packaged.
		Because the devices require high current and high voltages, and because the wafers are thin and difficult to hold down with a wafer chuck, probing can pose a danger to both the test instruments and the engineers who deploy them.
		According to Cascade's Sartor, testing of such devices today requires a detour from the normal design cycle, as engineers remove a "split"--a multidice section of the wafer--send it out for packaging and then test the packaged chips in specially constructed fixtures.
	www.eetimes.com /issue/na/showArticle.jhtml?articleID=199701461 (999 words)

	International Test Solutions - Probe Card Cleaning Technology
		International Test Solutions provides non-destructive probe card cleaning products used by semiconductor manufacturers to remove debris and contaminants generated during wafer level and burn-in/test socket testing.
		By removing loose debris and adherent contaminants in-line, the quality of the testing data is improved, the test equipment downtime is reduced, throughput is increased and manufacturing yields are improved.
		Probe Scrub™ is a multilayer probe card cleaning medium developed for collecting particulates and debris that accumulate on probes during wafer sort and effectively removing "weld nuggets" from the probe tip contact surface.
	www.inttest.com (305 words)

	ChipScale/0300-chip
		Stress testing is performed at wafer test to accelerate the failure of a die that may fail in early field life.
		An alternate to speed testing is the use of E-test to bin wafers by speed grade.
		Wafers not suitable for KGD §ow can be screened out at E-test and routed to conventional packaging that includes full testing plus burn-in.
	www.chipscalereview.com /issues/0300/chip23.html (1017 words)

	Colibrys - Test and assembly facility - Colibrys is a world leading supplier of standard MEMS products and innovative ...
		Colibrys - Test and assembly facility - Colibrys is a world leading supplier of standard MEMS products and innovative custom MEMS solutions.
		Colibrys is able to undertake assembly, test, product screening and burn-in within the same factory.
		This is often highly attractive in winning new business from customers who ultimately would like to have a ‘solution’ and make the MEMS experience invisible.
	www.colibrys.ch /e/page/171 (119 words)

	Electroglas: Company History
		The company's dedication to improving customer test efficiency has also resulted in the delivery of visionary prober-based solutions for both sort floor and final test applications.
		The EG5300e, a high-throughput, automatic prober for parametric testing on 300mm wafers is also introduced.
		is introduced to address the demands of testing fine pitch devices, semiconductors with copper interconnects and low-k dielectric processes, and other advanced applications.
	www.electroglas.com /company/history.shtml (595 words)

	SAMSUNG's Digital World - Semiconductor \| System LSI (Site not responding. Last check: )
		Upon completion, wafers are then sent to an IC packaging company to be sliced into individual die that are packaged in casings often made of ceramic.
		One wafer can yield hundreds or even thousands of die, each of which must then undergo final testing to confirm its integrity.
		Wafer foundry services have evolved over the years from a singular focus on wafer production to a one-stop service that covers the entire IC manufacturing process.
	www.samsung.com /Products/Semiconductor/ASIC/FoundryService/index.htm (888 words)

Try your search on: Qwika (all wikis)