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Topic: XAUI

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	XAUI: Curing Internal Speed Blockages (Site not responding. Last check: 2007-11-03)
		XAUI was originally conceived as a chip-to-chip connection scheme for use on PCBs.
		After using XAUI to connect chips to chips and boards to boards, the next logical place for developers to apply this technology is to connect boxes to boxes.
		In the latter case, XAUI is used as the coding sublayer for a coarse wavelength division multiplexed (CWDM) fiber-optic PHY.
	www.commsdesign.com /printableArticle?articleID=16503592 (2086 words)

	XAUI - Wikipedia, the free encyclopedia
		XAUI (a concatenation of the Roman numeral X, meaning ten, and the initials of "Attachment Unit Interface") is a standard for connecting 10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on a printed circuit board.
		For example, a network switch may have many 10GbE ports, perhaps of different types, but must have the capability to connect any port to any other port.
		If all these ports are XAUI types, then the same electronic switches can be used to interconnect any of the ports using a minimum number of circuit wires.
	en.wikipedia.org /wiki/XAUI (162 words)

	MoreThanIP PRODUCTS/10G XAUI (Site not responding. Last check: 2007-11-03)
		XAUI (10 Gigabit Attachment Unit Interface) provides a low pin count board level interface to connect a 10 Gigabit Ethernet MAC to a physical device such as an optical or a Xenpack, XPAK or X2 modules.
		Using a XAUI interface (rather than XGMII) on a 10 Gigabit MAC application simplifies the board design as the discrete Quad SERDES (Serializer/Deserializer) can typically be removed from the board, and as a XAUI interface implements 16 differential PCML (Pseudo Common Mode Logic) signals versus 72 HSTL Class I signals of a XGMII interface.
		MorethanIP XAUI Cores can already be used for 10 Gigabit applications design, which provide significant time-to-market advantage, and, through a strong technical partnership with Altera, MorethanIP is able to provide verified solutions to ensure design success.
	www.morethanip.com /products/10g/xaui_index.shtml (310 words)

	WAVECREST Market Applications
		XAUI is a layer in which 10 Gigabit Ethernet service providers implement 10 Gigabit Ethernet components.
		The XAUI interface is subjected to several performance metrics that attempt to quantify interoperability with other XAUI components.
		XAUI jitter measurements are made using Wavecrest's patented algorithms for Total Jitter separation into DJ, RJ, DCDandISI and PJ.
	www.wavecrest.com /market_applications/XAUI.htm (188 words)

	Product Folder : TLK3114SA - 10 Gbps XAUI Transceiver
		XAUI interpacket gap /A/, /K/, and /R/ code generation and stripping
		The TLK3114SA device supports both the 32-bit data path, 4-bit control, 10-gigabit media independent interface (XGMII), and the extended auxiliary unit interface (XAUI) specified in the IEEE 802.3ae 10-Gigabit Ethernet standard.
		If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.
	focus.ti.com /docs/prod/folders/print/tlk3114sa.html (591 words)

	10 Gigabit Ethernet (10GbE) - 10 Gbps (Site not responding. Last check: 2007-11-03)
		Pronounced “Zowie” - the XAUI is the 10GbE MDI.
		The XAUI is an interface extender, and the interface, which it extends, is the XGMII.
		The XAUI is a full duplex interface that uses four (4) self-clocked serial differential links in each direction to achieve 10 Gb/s data throughput.
	www.infocellar.com /networks/new-tech/GbE/GbE.htm (1856 words)

	i/oZONE Product Review: Texas Instruments TLK3118 Quad XAUI Backplane SerDes
		Manufactured in TI's advanced 130nm CMOS technology, the TLK3118 is a flexible, redundant XAUI serial transceiver compliant with the IEEE 802.3ae specification for 10 Gigabit Ethernet.
		They have taken a conscientious and solid approach to the challenges of shipping 3+ Gbit/s across the often-hostile environments found in backplanes, with a programmable analog equalizer on the receiver and a programmable pre-emphasis circuit on driver side.
		So far, TI has found the fastest slew rate almost always works best, but I'm willing to wager that somebody out there will be able to use a slower rise time to their advantage.
	www.analogzone.com /iop_0419.htm (1037 words)

	Synopsys Products: DesignWare Cores
		The DesignWare® XAUI PHY intellectual property (IP) is designed for use in any networking or high-end computing system-on-chip (SoC) solutions.
		Designed for the latest high speed backplanes, the XAUI PHY supports the 10 Gigabit Ethernet standards that are commonly used in high speed communications applications.
		To handle increasing communication system speeds, the XAUI standard was designed to take a 10 Gbps serial stream and divided into four 2.5Gbps serial streams that run over copper traces and chip to chip connections using 8B10B coding at 3.125Gbaud.
	www.synopsys.com /products/designware/docs/ds/c/dwc_xaui_phy.html (227 words)

	Marvell: Press and Investor News (Site not responding. Last check: 2007-11-03)
		The two XAUI interfaces of the device can be connected to each other to implement full bi-directional XAUI-to-XAUI transceiver for repeater applications.
		The eight lanes can be configured as two groups of four to implement two XAUI interfaces or can be configured independently as eight separate lanes.
		The XAUI modes of operation support 10 Gigabit Ethernet applications at 3.125 Gbps and 10 Gigabit Fiber Channel applications at 3.1875 Gbps.
	www.marvell.com /press/pressNewsDisplay.do?releaseID=67 (863 words)

	Aeluros Products - Puma 10 Gbps to XAUI PHY Transceiver ICs (Site not responding. Last check: 2007-11-03)
		In WAN mode, the AEL1004 device receives a system signal at the standard XAUI data rate of 3.125 Gbps, provides a SONET-style framing implementation, and transmits line-side data at a SONET data rate of 9.953 Gbps, thereby expanding the applicability of 10 Gigabit Ethernet signaling to SONET-based networks.
		By addressing data rates of both 10.3125 Gbps and 10.51875 Gbps on the line side and XAUI data rates of both 3.125 Gbps and 3.1875 Gbps, Puma devices are able to address applications compliant to both the IEEE 802.3ae 10 Gigabit Ethernet and INCITS 10 Gigabit Fibre Channel standards.
		The XAUI interface is capable of driving 3 Gbps signals across 40 inches of FR-4 backplane, while interoperability of both interfaces has been verified with numerous silicon, module, and system vendors.
	www.aeluros.com /products-puma.html (737 words)

	Mindspeed™ Participates in World's Largest Multi-Vendor
		With data rates up to 3.4 Gbps per channel, high-speed XAUI redundancy, traffic monitoring, and low jitter, the M27205 meets the high-performance and high-reliability demands of carrier-class 10 Gigabit Ethernet equipment.
		XAUI is a low-pin-count electrical interface that consists of four differential channels called "lanes" operating at 3.125 Gbps each to provide an aggregate raw bandwidth of 12.5 Gbps, or 10 Gbps of Ethernet data.
		XAUI was defined to extend the optical module system interface reach inside a network element up to 20 inches through a standard FR-4 board and two connectors.
	www.mindspeed.com /mspd/news_events/news_files/05072002-1.htm (1451 words)

	TechOnLine - XAUI: An Overview (Site not responding. Last check: 2007-11-03)
		153 KB This white paper is designed to provide a general overview of the XAUI interface (pronounced "zowie"), which is part of the impending 10 Gigabit Ethernet standard.
		Details of the technology are found in clauses 47 and 48 of the 10 Gb Ethernet standard (IEEE 802.3ae), which is currently on track for IEEE approval by mid-2002.
		This paper by the 10 Gigabit Ethernet Alliance, a group of companies interested in promoting the forthcoming standard, describes XAUI's role in the 10 Gigabit Ethernet architecture and provides a description of its basic operation.
	www.techonline.com /community/tech_group/comm/tech_paper/21173 (122 words)

	10-Gigabit Ethernet XAUI (Site not responding. Last check: 2007-11-03)
		FPGAs provide very high performance, allowing designs to be implemented in less-expensive and lower-speed-grade devices.
		Altera’s Stratix II GX and Stratix GX devices are equipped with built-in transceivers that provide a dedicated mode for implementing the XAUI interface.
		Embedded within this transceiver are dedicated rate-matching first-in, first-out (FIFO) buffers, 8b/10b encoding and decoding functions, and word-alignment functions, all controlled by dedicated XAUI state machines.
	www.altera.com /technology/high_speed/protocols/10gb_ethernet/pro-10gb_ethernet.html (226 words)

	SOCcentral: Xilinx Provides Proven XAUI Solution for 10 Gigabit Ethernet Applications (Xilinx, Inc. 2390) (Site not responding. Last check: 2007-11-03)
		The new 1000BASE-X PCS/PMA and XAUI cores can be used in the development of emerging 1 and 10 Gigabit networking and telecom equipment.
		The XAUI core utilizes four channel-bonded Virtex-II Pro RocketIO transceivers to provide a 4-lane high-speed serial interface offering 10 Gigabits per second (Gbps) total data throughput.
		Included with the XAUI core are the XGMII Extender Sublayers (DTE and PHY XGXS) and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3ae-2002.
	www.soccentral.com /results.asp?entryID=2390 (612 words)

	Synopsys Announces Low Power PHY IP for PCI Express, XAUI and SATA
		These PHYs are based on an advanced analog architecture designed to scale to the next generation of data rates and process technologies as new high-speed SERDES protocols evolve.
		"With the addition of the new PCIe, SATA and XAUI PHYs to its IP portfolio, Synopsys clearly demonstrates its commitment to delivering low-power, high-performance interconnects," said Jag Bolaria Senior Analyst at The Linley Group.
		The DesignWare SATA and XAUI PHYs are currently available in limited production for 130- and 90-nm process technologies.
	www.synopsys.com /news/announce/press2005/snps_lowpwr_phyip_pr.html (796 words)

	The Data Center Journal - Quake launches ultra low power 10G serial-to-XAUI PHY device (Site not responding. Last check: 2007-11-03)
		The QT2022 converts four 3.125 Gb/s XAUI lanes into a serial 10.3-10.57 Gb/s data stream.
		The serial interface is compliant with the XFI requirements and can be connected to an electro-optical interface or an XFP module.
		The output amplitude of both the XAUI and the serial interfaces can be adjusted for optimal power and performance.
	www.datacenterjournal.com /News/Article.asp?article_id=77 (785 words)

	Lattice Demonstrates Robust Interoperability at University of New Hampshire XAUI Plugfest (Site not responding. Last check: 2007-11-03)
		The tests were conducted at the recent XAUI PlugFest at the InterOperability Laboratory (IOL) of the University of New Hampshire's Research Computing Center.
		It is targeted at XAUI- and Fibre Channel-based backplane applications.
		The ORT82G5 devices were socketed on a paddle-board equipped with a Tyco HM-Zd connecter for easy interfacing to the Tyco Electronics XAUI HM-Zd Interoperability test platform.
	www.latticesemi.com /corporate/press/product/2003/pr080703.cfm (1009 words)

	Tektronix: Applications & Technologies > 10 Gigabit Attachment Unit Interface (XAUI) Design Solutions
		The 10 Gigabit Attachment Unit Interface (XAUI) is a technical innovation that dramatically improves and simplifies the routing of electrical interconnections.
		But, with it comes interoperability and compliance issues that demand powerful test and measurement equipment.
		Tektronix' comprehensive, integrated tool set - oscilloscopes, probes and software - enables designers to resolve these issues quickly and efficiently so that they can easily implement XAUI into their designs.
	www.tek.com /Measurement/Solutions/serial_data/xaui.html (116 words)

	Xilinx provides proven XAUI solution for 10 Gigabit Ethernet applications. \| Computers and Office Automation Industries (Site not responding. Last check: 2007-11-03)
		Xilinx also announced successful interoperability testing of its 10 Gigabit Attachment Unit Interface (XAUI) IP core with a number of 3rd party vendors during several group test sessions.
		By successfully completing the UNH IEEE 802.3 conformance tests for Ethernet MAC and by demonstrating interoperability with networking equipment incorporating standard gigabit Ethernet devices, Xilinx is providing IP solutions that significantly reduce the hardware testing burden for customers and accelerate their time to market.
		The 1000BASE-X core is designed to the IEEE 802.3-2002 standard, and is available with a choice of two PHY side interfaces: a 1000BASE-X PCS with Ten Bit Interface (TBI), or an integrated 1000BASE-X PCS/PMA which allows designers to simplify their board designs.
	www.allbusiness.com /periodicals/article/596651-1.html (855 words)

	Switch Fabric, Traffic Manager, XAUI, Network Processor, Line Card (Site not responding. Last check: 2007-11-03)
		With its 16 SerDes interfaces it employs the leading edge serial technologies which is used to implement up to four 12.5 Gbps XAUI channels.
		The coupling of the flow control to the switch buffer state, allows the switch to operate efficiently under extreme bursty conditions and at high utilization levels.
		Improves the efficiency of the fabric links, by adjusting the used cell size to the needs of the frame under transmission by the network processor unit (NPU) or a traffic manager (TM).
	www.tera-chip.com /interface.asp (384 words)

	XGMII and XGMII Interfaces
		The primary application is as a dual XGMII to dual XAUI transceiver for use in 10 Gigabit Ethernet and 10 Gigabit Fibre Channel applications, however each parallel-to-serial channel can be configured to support a number of applications with data rates ranging from 0.95 to 3.25 Gb/s.
		This device is ideally suited for connecting between high speed serial backplanes or optical modules and common 8-bit or 10-bit parallel interfaces found on many of today's ASICs.
		The VSC7281 features a single XGMII parallel port that can be switched between one of two XAUI serial ports.
	www.nuhorizons.com /products/NewProducts/poq19/vitesse.html (411 words)

	Mindspeed Demonstrates Feasibility Of XAUI 10 Gigabit Ethernet Technology And Interoperability With Blaze And Alvesta ...
		In a test at the University of New Hampshire InterOperability Laboratory in July, Mindspeed, Tyco, Blaze, and other vendors proved that their XAUI devices designed to the IEEE 802.3ae 10 Gigabit Ethernet specification were able to successfully communicate with each other, demonstrating the technical feasibility of XAUI.
		As a result, the 10 Gigabit Ethernet Task Force unanimously voted that the XAUI technology is feasible, paving the way for its inclusion in the emerging 10 Gigabit Ethernet standard.
		"We are very pleased that Mindspeed participated in this important interoperability test, demonstrating XAUI interoperability in a rigorous environment," said John D'Ambrosia, chair of the 10 Gigabit Ethernet XAUI Interoperability Group and manager of semiconductor relations for Tyco Electronics Corporation.
	www.mindspeed.com /mspd/news_events/news_files/08292001-1.htm (1063 words)

	Middle East Open Encyclopedia: XAUI (Site not responding. Last check: 2007-11-03)
		This is an extract from The Middle East Open Encyclopedia, made possible through the Wikimedia Foundation.
		Iraq Museum International always displays the most recent published revision of the source article, XAUI; all previous versions may be viewed here.
		They link directly to authoring tools for you to start writing a particular article.
	www.baghdadmuseum.org /ref?title=XAUI (286 words)

	Electrical Engineering Glossary Definition for XAUI - Maxim/Dallas
		Maxim/Dallas > Glossary of EE Terms > XAUI
		XAUI (pronounced "Zowie") is a ten Gigabit/second interface.
		The XAUI is designed as an interface extender, and the interface which it extends is the XGMII, the ten Gigabit Media Independent Interface.
	www.maxim-ic.com /glossary/index.cfm/Ac/V/ID/343/Tm/XAUI (107 words)

	Light Reading - Chips, Components & Subsystems - Xilinx Passes XAUI Test - Telecom News Wire
		The new 1000BASE-X PCS/PMA and XAUI cores can be used in the development of emerging 1 & 10 Gigabit networking and telecom equipment.
		The XAUI core utilizes four channel-bonded Virtex-II Pro RocketIO(TM) transceivers to provide a 4-lane high-speed serial interface offering 10 Gigabits per second (Gbps) total data throughput.
		The Ethernet 1000BASE-X PCS/PMA and XAUI cores are available now as LogiCORE(TM) products under the terms of the SignOnce IP license and are downloadable from www.xilinx.com/connectivity.
	www.lightreading.com /document.asp?doc_id=36369 (1094 words)

	OpenChoice IP Catalog T-CS-ET-0017-100 (Site not responding. Last check: 2007-11-03)
		The XAUI PCS takes the packet data from a 10 Gigabit Ethernet MAC and performs the idle conversion and code-group generation before performing 8B/10B encoding.
		On the receive path, the XAUI PCS takes the unaligned data from the four SerDes modules, re-aligns each lane to the 8B/10B boundary, decodes the data and then aligns all four lanes.
		The decoded and aligned data is then passed to the MAC.
	www.cadence.com /products/ip/ipview.aspx?ip=T-CS-ET-0017-100 (144 words)

	PMC-Sierra intros enterprise 10 Gigabit Ethernet LANPHY device to support XAUI-based optics. \| Computers and Office ...
		The XAUI interface standard, adopted by this style of optical module, is a very robust board-level interface which provides an extra degree of freedom in the physical design of a platform.
		The XAUI interface for the S/UNI 1x10GE-XP is leveraged from PMC-Sierra's industry proven four channel PM8355 QuadPHY II XAUI to XGMII Serializer/Deserializer (SERDES) that provides low power operation and exceptional performance.
		The S/UNI 1x10GE-XP has a SPI-4.2/PL4 system-side interface and a XAUI line-side interface with integrated standards compliant 10GE MAC and PCS blocks (figure 3).
	www.allbusiness.com /periodicals/article/325202-1.html (836 words)

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